From: klehman <klehman9@comcast.net>
Date: Fri, 1 Oct 2021 22:01:47 +0000 (-0400)
Subject: fix for self.rom core
X-Git-Tag: sv_maxu_works-initial~795
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6beaa06b12bd67fcd28999ef7cfe716195f351f;p=openpower-isa.git

fix for self.rom core
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index bb43c558..a6ecd9f0 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -402,7 +402,7 @@ class TestRunnerBase(FHDLTestCase):
         # optionally, if a wishbone-based ROM is passed in, run that as an
         # extra emulated process
         if self.rom is not None:
-            dcache = core.fus.fus["mmu0"].alu.dcache
+            dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))