From: Francis Lam <flam@alum.mit.edu>
Date: Sun, 14 Jul 2019 19:27:28 +0000 (-0700)
Subject: soc: cores: fix name of EHXPLLL output clock in ECP5PLL
X-Git-Tag: 24jan2021_ls180~1100^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6c743915acb309928dc2f267c8e324694a71feb;p=litex.git

soc: cores: fix name of EHXPLLL output clock in ECP5PLL
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index eb44d849..d5a8f492 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -476,7 +476,7 @@ class ECP5PLL(Module):
             p_CLKI_DIV=1,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
-            n_to_l = {0: "P", 1: "S", 2: "OS2"}
+            n_to_l = {0: "P", 1: "S", 2: "S2"}
             self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
             self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)]
             self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0