From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 17:07:03 +0000 (-0700)
Subject: Revert "Update doc for equiv_opt"
X-Git-Tag: working-ls180~1001^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6d15c9aade55a87595693ecb9170ae8b595e28c;p=yosys.git

Revert "Update doc for equiv_opt"

This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.
---

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 4ab5b1a3e..9fe3bbd57 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -32,8 +32,7 @@ struct EquivOptPass:public ScriptPass
 		log("\n");
 		log("    equiv_opt [options] [command]\n");
 		log("\n");
-		log("This command uses temporal induction to check circuit equivalence before and\n");
-                log("after an optimization pass.\n");
+		log("This command checks circuit equivalence before and after an optimization pass.\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
@@ -157,7 +156,7 @@ struct EquivOptPass:public ScriptPass
 		if (check_label("prove")) {
 			if (multiclock || help_mode)
 				run("clk2fflogic", "(only with -multiclock)");
-			if (!multiclock || help_mode)
+			else
 				run("async2sync", "(only without -multiclock)");
 			run("equiv_make gold gate equiv");
 			if (help_mode)