From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 20:26:19 +0000 (+0100)
Subject: move FPSCData to separate module
X-Git-Tag: ls180-24jan2020~604
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6d5461c24b2bca980f26fb4952d2a8cdf7530eb;p=ieee754fpu.git

move FPSCData to separate module
---

diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py
index 52bae10a..bf4742e9 100644
--- a/src/ieee754/fpcommon/denorm.py
+++ b/src/ieee754/fpcommon/denorm.py
@@ -10,36 +10,7 @@ from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.fpbase import FPNumBase
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class FPSCData:
-
-    def __init__(self, pspec, m_extra):
-        width = pspec.width
-        # NOTE: difference between z and oz is that oz is created by
-        # special-cases module(s) and will propagate, along with its
-        # "bypass" signal out_do_z, through the pipeline, *disabling*
-        # all processing of all subsequent stages.
-        self.a = FPNumBaseRecord(width, m_extra, name="a")   # operand a
-        self.b = FPNumBaseRecord(width, m_extra, name="b")   # operand b
-        self.z = FPNumBaseRecord(width, False, name="z")     # denormed result
-        self.oz = Signal(width, reset_less=True)   # "finished" (bypass) result
-        self.out_do_z = Signal(reset_less=True)    # "bypass" enabled
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.a
-        yield from self.b
-        yield from self.z
-        yield self.oz
-        yield self.out_do_z
-        yield from self.ctx
-
-    def eq(self, i):
-        ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-               self.a.eq(i.a), self.b.eq(i.b), self.ctx.eq(i.ctx)]
-        return ret
+from ieee754.fpcommon.pscdata import FPSCData
 
 
 class FPAddDeNormMod(PipeModBase):
@@ -81,5 +52,3 @@ class FPAddDeNormMod(PipeModBase):
         comb += self.o.oz.eq(self.i.oz)
 
         return m
-
-
diff --git a/src/ieee754/fpcommon/pscdata.py b/src/ieee754/fpcommon/pscdata.py
new file mode 100644
index 00000000..da449d27
--- /dev/null
+++ b/src/ieee754/fpcommon/pscdata.py
@@ -0,0 +1,39 @@
+"""IEEE754 Floating Point Library
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+"""
+
+from nmigen import Signal
+from ieee754.fpcommon.fpbase import FPNumBaseRecord
+from ieee754.fpcommon.getop import FPPipeContext
+
+
+class FPSCData:
+
+    def __init__(self, pspec, m_extra):
+        width = pspec.width
+        # NOTE: difference between z and oz is that oz is created by
+        # special-cases module(s) and will propagate, along with its
+        # "bypass" signal out_do_z, through the pipeline, *disabling*
+        # all processing of all subsequent stages.
+        self.a = FPNumBaseRecord(width, m_extra, name="a")   # operand a
+        self.b = FPNumBaseRecord(width, m_extra, name="b")   # operand b
+        self.z = FPNumBaseRecord(width, False, name="z")     # denormed result
+        self.oz = Signal(width, reset_less=True)   # "finished" (bypass) result
+        self.out_do_z = Signal(reset_less=True)    # "bypass" enabled
+        self.ctx = FPPipeContext(pspec)
+        self.muxid = self.ctx.muxid
+
+    def __iter__(self):
+        yield from self.a
+        yield from self.b
+        yield from self.z
+        yield self.oz
+        yield self.out_do_z
+        yield from self.ctx
+
+    def eq(self, i):
+        ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+               self.a.eq(i.a), self.b.eq(i.b), self.ctx.eq(i.ctx)]
+        return ret