From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Wed, 28 Sep 2016 13:26:32 +0000 (+0200)
Subject: [ARC] Add simple shift/rotate ops.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6d66e907784830a1039d130ad35d500ea6dc005;p=gcc.git

[ARC] Add simple shift/rotate ops.

2016-09-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (*rotrsi3_cnt1): New pattern,
	(*ashlsi2_cnt1, *lshrsi3_cnt1, *ashrsi3_cnt1): Likewise.

From-SVN: r240576
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e1e8bc385cb..51afcec0737 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-09-29  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (*rotrsi3_cnt1): New pattern.
+	(*ashlsi2_cnt1, *lshrsi3_cnt1, *ashrsi3_cnt1): Likewise.
+
 2016-09-28  Nathan Sidwell  <nathan@acm.org>
 
 	* gimple-pretty-print.c (dump_gimple_call_args): Simplify "' "
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index ac7346bc0a6..715da315d76 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6190,6 +6190,46 @@
 		   (zero_extract:SI (match_dup 1) (match_dup 5) (match_dup 7)))])
    (match_dup 1)])
 
+(define_insn "*rotrsi3_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"             "=w")
+	(rotatert:SI (match_operand:SI 1 "register_operand" "c")
+		     (const_int 1)))]
+  ""
+  "ror %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "predicable" "no")
+   (set_attr "length" "4")])
+
+(define_insn "*ashlsi2_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"           "=Rcqq,w")
+	(ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
+		   (const_int 1)))]
+  ""
+  "asl%? %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "iscompact" "maybe,false")
+   (set_attr "predicable" "no,no")])
+
+(define_insn "*lshrsi3_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"             "=Rcqq,w")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
+		     (const_int 1)))]
+  ""
+  "lsr%? %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "iscompact" "maybe,false")
+   (set_attr "predicable" "no,no")])
+
+(define_insn "*ashrsi3_cnt1"
+  [(set (match_operand:SI 0 "dest_reg_operand"             "=Rcqq,w")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c")
+		     (const_int 1)))]
+  ""
+  "asr%? %0,%1%&"
+  [(set_attr "type" "shift")
+   (set_attr "iscompact" "maybe,false")
+   (set_attr "predicable" "no,no")])
+
 ;; include the arc-FPX instructions
 (include "fpx.md")