From: lkcl <lkcl@web>
Date: Fri, 8 Apr 2022 00:11:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2852
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6e56991f8ffb6fb7780fb51e38e87cd24ca2365;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 25f797934..ded4f7b35 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -253,7 +253,7 @@ Counter (aka "a Branch"), resulting in early-out
 opportunities
 * CTR-testing
 
-Both are outlined below.
+Both are outlined below, in later sections.
 
 # Horizontal-First and Vertical-First Modes
 
@@ -349,9 +349,9 @@ with LK, as follows:
 * `sv.bc` When LRu=0,LK=0, Link Register is not updated
 * `sv.bcl` When LRu=0,LK=1, Link Register is updated unconditionally
 * `sv.bcl/lru` When LRu=1,LK=1, Link Register will
-  only be updated if the Branch Condition succeeds.
+  only be updated if the Branch Condition fails.
 * `sv.bc/lru` When LRu=1,LK=0, Link Register will only be updated if
-  the Branch Condition fails.
+  the Branch Condition succeeds.
 
 This avoids
 destruction of LR during loops (particularly Vertical-First
@@ -622,12 +622,12 @@ for srcstep in range(VL):
     if SVCRf.scalar:
        break
 # loop finally done, now test if branch (and update LR)
-lr_ok <- SVRMmode.LRu
+lr_ok <- LK
 if cond_ok then
     if AA then NIA <-iea EXTS(BD || 0b00)
     else       NIA <-iea CIA + EXTS(BD || 0b00)
-    lr_ok <- ¬lr_ok
-if (LK & lr_ok) | (¬LK & lr_ok) then LR <-iea CIA + 4
+    if SVRMmode.LRu then lr_ok <- ¬lr_ok
+if lr_ok then LR <-iea CIA + 4
 ```
 
 Pseudocode for Vertical-First Mode:
@@ -748,10 +748,12 @@ for i in 0 to VL-1:
     ...
     ...
     cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
+    lr_ok <- LK
     if ctr_ok & cond_ok then
        NIA <-iea LR[0:61] || 0b00
-       lr_ok = ¬lr_ok
-    if (LK & lr_ok) | (¬LK & lr_ok) then LR <-iea CIA + 4
+       if SVRMmode.LRu then lr_ok <- ¬lr_ok
+    if lr_ok then LR <-iea CIA + 4
+    # if NIA modified exit loop
 ```
 
 The reason why should be clear from this being a Vector loop: