From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 30 Aug 2022 13:20:20 +0000 (+0100)
Subject: Revert "remove dead code, sv.svstep and sv.fcoss are now handled by CUSTOM_INSNS"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6e75e2bd8fc3b8a57d9222fa0f6fe1d7c343c3e;p=openpower-isa.git

Revert "remove dead code, sv.svstep and sv.fcoss are now handled by CUSTOM_INSNS"

This reverts commit cfd0215fc6f716317eb22d04d965028eb794965b.
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 0c3e3f87..53bc7728 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1340,6 +1340,27 @@ class SVP64Asm:
             if rc:
                 opcode |= 1  # Rc, bit 31.
             yield ".long 0x%x" % opcode
+        # sigh have to do svstep here manually for now...
+        elif v30b_op in ["svstep", "svstep."]:
+            insn = 22 << (31-5)          # opcode 22, bits 0-5
+            insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
+            insn |= int(v30b_newfields[1]) << (31-22)  # SVi      , bits 16-22
+            insn |= int(v30b_newfields[2]) << (31-25)  # vf       , bit  25
+            insn |= 0b10011 << (31-30)  # XO       , bits 26..30
+            if opcode == 'svstep.':
+                insn |= 1 << (31-31)     # Rc=1     , bit 31
+            log("svstep", bin(insn))
+            yield ".long 0x%x" % insn
+        # argh, sv.fcoss etc. need to be done manually
+        elif v30b_op in ["fcoss", "fcoss."]:
+            insn = 59 << (31-5)  # opcode 59, bits 0-5
+            insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
+            insn |= int(v30b_newfields[1]) << (31-20)  # RB       , bits 16-20
+            insn |= 0b1000101110 << (31-30)  # XO       , bits 21..30
+            if opcode == 'fcoss.':
+                insn |= 1 << (31-31)     # Rc=1     , bit 31
+            log("fcoss", bin(insn))
+            yield ".long 0x%x" % insn
         else:
             if not v30b_op.endswith('.'):
                 v30b_op += rc