From: Jacob Lifshay Date: Sun, 7 Jul 2019 07:10:12 +0000 (-0700) Subject: misc code cleanups X-Git-Tag: ls180-24jan2020~900 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6e8177ef601519b1ecf13f9246ec0eacc326d3c;p=ieee754fpu.git misc code cleanups --- diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 75a1b5c8..c1b5191b 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -21,9 +21,6 @@ right-hand-side of the comparison in the above formulas. from nmigen import (Elaboratable, Module, Signal, Const, Mux) import enum -# TODO, move to new (suitable) location -#from ieee754.fpcommon.getop import FPPipeContext - class DivPipeCoreConfig: """ Configuration for core of the div/rem/sqrt/rsqrt pipeline. @@ -103,17 +100,13 @@ class DivPipeCoreInputData: yield self.dividend yield self.divisor_radicand yield self.operation # FIXME: delete. already covered by self.ctx - return - yield self.z - yield self.out_do_z - yield self.oz - yield from self.ctx def eq(self, rhs): """ Assign member signals. """ return [self.dividend.eq(rhs.dividend), self.divisor_radicand.eq(rhs.divisor_radicand), - self.operation.eq(rhs.operation)] # FIXME: delete. + self.operation.eq(rhs.operation), # FIXME: delete. + ] class DivPipeCoreInterstageData: @@ -145,7 +138,7 @@ class DivPipeCoreInterstageData: """ Create a ``DivPipeCoreInterstageData`` instance. """ self.core_config = core_config self.divisor_radicand = Signal(core_config.bit_width, reset_less=True) - # XXX FIXME: delete. already covered by self.ctx.op + # FIXME: delete self.operation. already covered by self.ctx.op self.operation = DivPipeCoreOperation.create_signal(reset_less=True) self.quotient_root = Signal(core_config.bit_width, reset_less=True) self.root_times_radicand = Signal(core_config.bit_width * 2, @@ -156,7 +149,7 @@ class DivPipeCoreInterstageData: def __iter__(self): """ Get member signals. """ yield self.divisor_radicand - yield self.operation # XXX FIXME: delete. already in self.ctx.op + yield self.operation # FIXME: delete. already in self.ctx.op yield self.quotient_root yield self.root_times_radicand yield self.compare_lhs @@ -252,9 +245,6 @@ class DivPipeCoreSetupStage(Elaboratable): return m - # XXX in DivPipeSetupStage - DivPipeBaseStage._elaborate(self, m, platform) - class DivPipeCoreCalculateStage(Elaboratable): """ Calculate Stage of the core of the div/rem/sqrt/rsqrt pipeline. """ @@ -368,9 +358,6 @@ class DivPipeCoreCalculateStage(Elaboratable): | (next_bits << current_shift)) return m - # XXX in DivPipeCalculateStage - DivPipeBaseStage._elaborate(self, m, platform) - class DivPipeCoreFinalStage(Elaboratable): """ Final Stage of the core of the div/rem/sqrt/rsqrt pipeline. """ @@ -391,7 +378,7 @@ class DivPipeCoreFinalStage(Elaboratable): def setup(self, m, i): """ Pipeline stage setup. """ - m.submodules.div_pipe_core_setup = self + m.submodules.div_pipe_core_final = self m.d.comb += self.i.eq(i) def process(self, i): @@ -407,6 +394,3 @@ class DivPipeCoreFinalStage(Elaboratable): - self.i.compare_rhs) return m - - # XXX in DivPipeFinalStage - DivPipeBaseStage._elaborate(self, m, platform) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py index 02de78ed..aa0b9f90 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py @@ -1,22 +1,51 @@ # SPDX-License-Identifier: LGPL-2.1-or-later # See Notices.txt for copyright information """ div/rem/sqrt/rsqrt pipeline. """ + from .core import (DivPipeCoreConfig, DivPipeCoreInputData, DivPipeCoreInterstageData, DivPipeCoreOutputData) +from ieee754.fpcommon.getop import FPPipeContext + + +class DivPipeConfig: + """ Configuration for the div/rem/sqrt/rsqrt pipeline. + + :attribute pspec: FIXME: document + :attribute core_config: the ``DivPipeCoreConfig`` instance. + """ + + def __init__(self, pspec): + """ Create a ``DivPipeConfig`` instance. """ + self.pspec = pspec + # FIXME: get bit_width, fract_width, and log2_radix from pspec or pass + # in as arguments + self.core_config = DivPipeCoreConfig(bit_width, + fract_width, + log2_radix) class DivPipeBaseData: """ input data base type for ``DivPipe``. + + :attribute out_do_z: FIXME: document + :attribute oz: FIXME: document + :attribute ctx: FIXME: document + :attribute muxid: + FIXME: document + Alias of ``ctx.muxid``. + :attribute config: the ``DivPipeConfig`` instance. """ - def __init__(self, pspec): + def __init__(self, config): """ Create a ``DivPipeBaseData`` instance. """ - width = pspec['width'] + self.config = config + width = config.pspec['width'] self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.ctx = FPPipeContext(pspec) # context: muxid, operator etc. - self.muxid = self.ctx.muxid # annoying. complicated. + self.ctx = FPPipeContext(config.pspec) # context: muxid, operator etc. + # FIXME: add proper muxid explanation somewhere and refer to it here + self.muxid = self.ctx.muxid # annoying. complicated. def __iter__(self): """ Get member signals. """ @@ -31,18 +60,12 @@ class DivPipeBaseData: class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData): - """ input data type for ``DivPipe``. - """ + """ input data type for ``DivPipe``. """ - def __init__(self, core_config): + def __init__(self, config): """ Create a ``DivPipeInputData`` instance. """ - DivPipeCoreInputData.__init__(self, core_config) - DivPipeBaseData.__init__(self, pspec) # XXX TODO args - self.out_do_z = Signal(reset_less=True) - self.oz = Signal(width, reset_less=True) - - self.ctx = FPPipeContext(pspec) # context: muxid, operator etc. - self.muxid = self.ctx.muxid # annoying. complicated. + DivPipeCoreInputData.__init__(self, config.core_config) + DivPipeBaseData.__init__(self, config) def __iter__(self): """ Get member signals. """ @@ -51,60 +74,61 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData): def eq(self, rhs): """ Assign member signals. """ - return DivPipeBaseData.eq(self, rhs) + \ - DivPipeCoreInputData.eq(self, rhs) + return DivPipeCoreInputData.eq(self, rhs) + \ + DivPipeBaseData.eq(self, rhs) class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData): - """ interstage data type for ``DivPipe``. - - :attribute core_config: ``DivPipeCoreConfig`` instance describing the - configuration to be used. - """ + """ interstage data type for ``DivPipe``. """ - def __init__(self, core_config): - """ Create a ``DivPipeCoreInterstageData`` instance. """ - DivPipeCoreInterstageData.__init__(self, core_config) - DivPipeBaseData.__init__(self, pspec) # XXX TODO args + def __init__(self, config): + """ Create a ``DivPipeInterstageData`` instance. """ + DivPipeCoreInterstageData.__init__(self, config.core_config) + DivPipeBaseData.__init__(self, config) def __iter__(self): """ Get member signals. """ - yield from DivPipeInterstageData.__iter__(self) + yield from DivPipeCoreInterstageData.__iter__(self) yield from DivPipeBaseData.__iter__(self) def eq(self, rhs): """ Assign member signals. """ - return DivPipeBaseData.eq(self, rhs) + \ - DivPipeCoreInterstageData.eq(self, rhs) + return DivPipeCoreInterstageData.eq(self, rhs) + \ + DivPipeBaseData.eq(self, rhs) class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData): - """ interstage data type for ``DivPipe``. + """ output data type for ``DivPipe``. """ - :attribute core_config: ``DivPipeCoreConfig`` instance describing the - configuration to be used. - """ - - def __init__(self, core_config): - """ Create a ``DivPipeCoreOutputData`` instance. """ - DivPipeCoreOutputData.__init__(self, core_config) - DivPipeBaseData.__init__(self, pspec) # XXX TODO args + def __init__(self, config): + """ Create a ``DivPipeOutputData`` instance. """ + DivPipeCoreOutputData.__init__(self, config.core_config) + DivPipeBaseData.__init__(self, config) def __iter__(self): """ Get member signals. """ - yield from DivPipeOutputData.__iter__(self) + yield from DivPipeCoreOutputData.__iter__(self) yield from DivPipeBaseData.__iter__(self) def eq(self, rhs): """ Assign member signals. """ - return DivPipeBaseData.eq(self, rhs) + \ - DivPipeCoreOutputData.eq(self, rhs) + return DivPipeCoreOutputData.eq(self, rhs) + \ + DivPipeBaseData.eq(self, rhs) class DivPipeBaseStage: - """ Base Mix-in for DivPipe*Stage """ + """ Base Mix-in for DivPipe*Stage. """ def _elaborate(self, m, platform): m.d.comb += self.o.oz.eq(self.i.oz) m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) m.d.comb += self.o.ctx.eq(self.i.ctx) + +# FIXME: in DivPipeSetupStage.elaborate +# DivPipeBaseStage._elaborate(self, m, platform) + +# FIXME: in DivPipeCalculateStage.elaborate +# DivPipeBaseStage._elaborate(self, m, platform) + +# FIXME: in DivPipeFinalStage.elaborate +# DivPipeBaseStage._elaborate(self, m, platform)