From: Eddie Hung Date: Wed, 4 Dec 2019 03:21:47 +0000 (-0800) Subject: Cleanup X-Git-Tag: working-ls180~881^2^2~103 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6ee2fb4825de727cc18c222888c4c8832d6f26f;p=yosys.git Cleanup --- diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 2943ed90d..c6d24cf94 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -83,7 +83,7 @@ struct XAigerWriter dict> and_map; vector> ci_bits; vector> co_bits; - dict> ff_bits; + dict> ff_bits; dict arrival_times; vector> aig_gates; @@ -245,7 +245,7 @@ struct XAigerWriter unused_bits.erase(D); undriven_bits.erase(Q); alias_map[Q] = D; - auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, State::Sx))); + auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, 2))); log_assert(r.second); continue; } @@ -369,10 +369,16 @@ struct XAigerWriter it = cell->attributes.find(ID(abc9_init)); log_assert(it != cell->attributes.end()); log_assert(GetSize(it->second) == 1); - rhs.second = it->second[0]; + if (it->second[0] == State::S1) + rhs.second = 1; + else if (it->second[0] == State::S0) + rhs.second = 0; + else { + log_assert(it->second[0] == State::Sx); + rhs.second = 0; + } cell->attributes.erase(it); - auto arrival = r.first->second.second; if (arrival) arrival_times[d] = arrival; @@ -815,13 +821,8 @@ struct XAigerWriter int mergeability = i.second.first; log_assert(mergeability > 0); write_r_buffer(mergeability); - State init = i.second.second; - if (init == State::S1) - write_s_buffer(1); - else if (init == State::S0) - write_s_buffer(0); - else - write_s_buffer(0); + int init = i.second.second; + write_s_buffer(init); write_i_buffer(arrival_times.at(bit, 0)); //write_o_buffer(0); }