From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 30 Jun 2017 17:41:14 +0000 (+0200)
Subject: soc/interconnect/wishbonebridge: reset_less optimizations
X-Git-Tag: 24jan2021_ls180~1822
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6f6d7b491f0c8227e28e171eea84d72bcb744e6;p=litex.git

soc/interconnect/wishbonebridge: reset_less optimizations
---

diff --git a/litex/soc/interconnect/wishbonebridge.py b/litex/soc/interconnect/wishbonebridge.py
index b3be5bd8..b9f9d109 100644
--- a/litex/soc/interconnect/wishbonebridge.py
+++ b/litex/soc/interconnect/wishbonebridge.py
@@ -19,7 +19,7 @@ class WishboneStreamingBridge(Module):
 
         # # #
 
-        byte_counter = Signal(3)
+        byte_counter = Signal(3, reset_less=True)
         byte_counter_reset = Signal()
         byte_counter_ce = Signal()
         self.sync += \
@@ -29,7 +29,7 @@ class WishboneStreamingBridge(Module):
                 byte_counter.eq(byte_counter + 1)
             )
 
-        word_counter = Signal(3)
+        word_counter = Signal(3, reset_less=True)
         word_counter_reset = Signal()
         word_counter_ce = Signal()
         self.sync += \
@@ -39,16 +39,16 @@ class WishboneStreamingBridge(Module):
                 word_counter.eq(word_counter + 1)
             )
 
-        cmd = Signal(8)
+        cmd = Signal(8, reset_less=True)
         cmd_ce = Signal()
 
-        length = Signal(8)
+        length = Signal(8, reset_less=True)
         length_ce = Signal()
 
-        address = Signal(32)
+        address = Signal(32, reset_less=True)
         address_ce = Signal()
 
-        data = Signal(32)
+        data = Signal(32, reset_less=True)
         rx_data_ce = Signal()
         tx_data_ce = Signal()