From: lkcl <lkcl@web>
Date: Sun, 26 Mar 2023 11:24:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls001_v3~59
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6fcf3b4042c537b9da03c72b38f86014bff0af7;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn
index 4f29019a6..9ce790e97 100644
--- a/openpower/sv/rfc/ls008.mdwn
+++ b/openpower/sv/rfc/ls008.mdwn
@@ -137,7 +137,7 @@ SVL-Form
 Pseudo-code:
 
 ```
-    overflow <- 0b0
+    overflow <- 0b0    # sets CR.SO if set and if Rc=1
     VLimm <- SVi + 1
     # set or get MVL
     if ms = 1 then MVL <- VLimm[0:6]
@@ -162,7 +162,7 @@ Pseudo-code:
     SVSTATE[7:13] <- VL
     if _RT != 0 then
        GPR(_RT) <- [0]*57 || VL
-    if ((¬vs) & ¬(ms)) = 0 then
+    if ((¬vs) & ¬(ms)) = 0 then
         # set requested Vertical-First mode, clear persist
         SVSTATE[63] <- vf
         SVSTATE[62] <- 0b0
@@ -174,6 +174,36 @@ Special Registers Altered:
     CR0                     (if Rc=1)
 ```
 
+* `SVi` - bits 16-22 - an immediate operand for setting MVL and/or VL
+* `ms` - bit 23 - allows for setting of MVL
+* `vs` - bit 24 - allows for setting of VL
+* `vf` - bit 25 - sets "Vertical First Mode".
+
+Note that in immediate setting mode VL and MVL start from **one**
+but that this is compensated for in the assembly notation.
+i.e. that an immediate value of 1 in assembler notation
+actually places the value 0b0000000 in the `SVi` field bits:
+on execution the `setvl` instruction adds one to the decoded
+`SVi` field bits, resulting in
+VL/MVL being set to 1. This allows VL to be set to values
+ranging from 1 to 128 with only 7 bits instead of 8.
+Setting VL/MVL
+to 0 would result in all Vector operations becoming `nop`.  If this is
+truly desired (nop behaviour) then setting VL and MVL to zero is to be
+done via the [[SVSTATE SPR|sv/sprs]].
+
+Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
+
+    setvli   VL=8   : setvl  r0, r0, VL=8, vf=0, vs=1, ms=0
+    setvli.  VL=8   : setvl. r0, r0, VL=8, vf=0, vs=1, ms=0
+    setmvli  MVL=8  : setvl  r0, r0, MVL=8, vf=0, vs=0, ms=1
+    setmvli. MVL=8  : setvl. r0, r0, MVL=8, vf=0, vs=0, ms=1
+
+Additional pseudo-op for obtaining VL without modifying it (or any state):
+
+    getvl  r5      : setvl  r5, r0, vf=0, vs=0, ms=0
+    getvl. r5      : setvl. r5, r0, vf=0, vs=0, ms=0
+
 -------------
 
 \newpage{}