From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 18:37:45 +0000 (-0800)
Subject: Add abc9.v testcase to simple_abc9
X-Git-Tag: working-ls180~1237^2~282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6fd057eda5dba371ff9c1142019b801bee81111;p=yosys.git

Add abc9.v testcase to simple_abc9
---

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 2d9aea366..d387b99eb 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -1,6 +1,48 @@
-module top(input [1:0] a, output [1:0] b, output c, output d, output e);
+module abc9_test001(input a, output o);
+assign o = a;
+endmodule
+
+module abc9_test002(input [1:0] a, output o);
+assign o = a[1];
+endmodule
+
+module abc9_test003(input [1:0] a, output [1:0] o);
+assign o = a;
+endmodule
+
+module abc9_test004(input [1:0] a, output o);
+assign o = ^a;
+endmodule
+
+module abc9_test005(input [1:0] a, output o, output p);
+assign o = ^a;
+assign p = ~o;
+endmodule
+
+module abc9_test006(input [1:0] a, output [2:0] o);
+assign o[0] = ^a;
+assign o[1] = ~o[0];
+assign o[2] = o[1];
+endmodule
+
+module abc9_test007(input a, output o);
+wire b, c;
+assign c = ~a;
+assign b = c;
+abc9_test007_sub s(b, o);
+endmodule
+
+module abc9_test007_sub(input a, output b);
 assign b = a;
-assign c = ^a;
-assign d = ~c;
-assign e = d;
+endmodule
+
+module abc9_test008(input a, output o);
+wire b, c;
+assign b = ~a;
+assign c = b;
+abc9_test008_sub s(b, o);
+endmodule
+
+module abc9_test008_sub(input a, output b);
+assign b = ~a;
 endmodule