From: Luke Kenneth Casson Leighton Date: Fri, 29 Apr 2022 09:32:24 +0000 (+0100) Subject: add option to set small cache sizes in X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c703e816770b6083cce8f3ddf8d757d211b775f4;p=soc.git add option to set small cache sizes in issuer_verilog.py --- diff --git a/Makefile b/Makefile index 8d379590..2a6409b6 100644 --- a/Makefile +++ b/Makefile @@ -65,11 +65,21 @@ microwatt_external_core: microwatt_external_core_spi: python3 src/soc/simple/issuer_verilog.py --microwatt-compat \ + --small-cache \ --enable-mmu \ --pc-reset 0x10000000 \ external_core_top.v +# microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just) microwatt_external_core_bram: + python3 src/soc/simple/issuer_verilog.py --microwatt-compat \ + --small-cache \ + --enable-mmu \ + --pc-reset 0xFF000000 \ + external_core_top.v + +# microwatt-compatible core with larger cache size (experiment on arty) +microwatt_external_core_bram_arty: python3 src/soc/simple/issuer_verilog.py --microwatt-compat \ --enable-mmu \ --pc-reset 0xFF000000 \ diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 39578ebc..82b983bd 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -741,18 +741,36 @@ class DCache(Elaboratable, DCacheConfig): self.log_out = Signal(20) + # test if small cache to be enabled + self.small_cache = (hasattr(pspec, "small_cache") and + (pspec.small_cache == True)) # test if microwatt compatibility is to be enabled self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and (pspec.microwatt_compat == True)) + XLEN = pspec.XLEN + TLB_SET_SIZE = 16 + TLB_NUM_WAYS = 2 + NUM_LINES = 16 + NUM_WAYS = 2 + + if self.small_cache: + # reduce way sizes and num lines to ridiculously small + TLB_SET_SIZE = 2 + TLB_NUM_WAYS = 1 + NUM_LINES = 2 + NUM_WAYS = 1 if self.microwatt_compat: - # reduce way sizes and num lines - super().__init__(NUM_LINES = 2, - NUM_WAYS = 1, - TLB_NUM_WAYS = 1, - TLB_SET_SIZE=2) # XXX needs device-tree entry - else: - super().__init__() + # reduce way sizes + NUM_WAYS = 1 + TLB_NUM_WAYS = 1 + + super().__init__(TLB_SET_SIZE=TLB_SET_SIZE, + # XLEN=XLEN, # TODO + TLB_NUM_WAYS = TLB_NUM_WAYS, + NUM_LINES = NUM_LINES, + NUM_WAYS = NUM_WAYS + ) def stage_0(self, m, r0, r1, r0_full): """Latch the request in r0.req as long as we're not stalling @@ -1593,7 +1611,7 @@ class DCache(Elaboratable, DCacheConfig): # If we are still sending requests, was one accepted? with m.If((~bus.stall) & r1.wb.stb): - # That was the last word? We are done sending. Clear stb + # That was the last word? We are done sending. Clear stb # sigh - reconstruct wb adr with 3 extra 0s at front wb_adr = Cat(Const(0, self.ROW_OFF_BITS), r1.wb.adr) with m.If(self.is_last_row_addr(wb_adr, r1.end_row_ix)): diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index b0b674c8..ff45332d 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -335,22 +335,33 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig): # use FetchUnitInterface, helps keep some unit tests running self.use_fetch_iface = False - # test if microwatt compatibility is to be enabled + # test if small cache to be enabled + self.small_cache = (hasattr(pspec, "small_cache") and + (pspec.small_cache == True)) + # test if microwatt compatibility to be enabled self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and (pspec.microwatt_compat == True)) XLEN = pspec.XLEN - + LINE_SIZE = 64 + TLB_SIZE = 16 + NUM_LINES = 16 + NUM_WAYS = 2 + if self.small_cache: + # reduce way sizes and num lines to ridiculously small + NUM_LINES = 2 + NUM_WAYS = 1 + TLB_SIZE = 2 if self.microwatt_compat: - # reduce way sizes and num lines - ICacheConfig.__init__(self, LINE_SIZE=XLEN, - XLEN=XLEN, - NUM_LINES = 2, - NUM_WAYS = 1, - TLB_SIZE=2 # needs device-tree update - ) - else: - ICacheConfig.__init__(self, LINE_SIZE=XLEN, XLEN=XLEN) + # reduce way sizes + NUM_WAYS = 1 + + ICacheConfig.__init__(self, LINE_SIZE=LINE_SIZE, + XLEN=XLEN, + NUM_LINES = NUM_LINES, + NUM_WAYS = NUM_WAYS, + TLB_SIZE=TLB_SIZE + ) def use_fetch_interface(self): self.use_fetch_iface = True diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 82639644..b4ec9e53 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -77,6 +77,11 @@ if __name__ == '__main__': action="store_true", help="generate old microwatt-compatible interface", default=False) + # small cache option + parser.add_argument("--small-cache", dest='smallcache', + action="store_true", + help="generate small caches", + default=False) # allow overlaps in TestIssuer parser.add_argument("--allow-overlap", dest='allow_overlap', @@ -150,6 +155,7 @@ if __name__ == '__main__': microwatt_compat=args.mwcompat, # microwatt compatible microwatt_old=args.old_mwcompat, # old microwatt api microwatt_debug=args.mwdebug, # microwatt debug signals + small_cache=args.smallcache, # small cache/TLB sizes allow_overlap=args.allow_overlap, # allow overlap units=units, msr_reset=msr_reset, @@ -172,6 +178,7 @@ if __name__ == '__main__': print("Microwatt compatibility", pspec.__dict__["microwatt_compat"]) print("Old Microwatt compatibility", pspec.__dict__["microwatt_old"]) print("Microwatt debug", pspec.__dict__["microwatt_debug"]) + print("Small Cache/TLB", pspec.__dict__["small_cache"]) if args.mwcompat: dut = TestIssuerInternal(pspec)