From: Marcelina Koƛcielnicka Date: Sat, 22 May 2021 14:36:50 +0000 (+0200) Subject: kernel/mem: Add a check() function. X-Git-Tag: yosys-0.10~198 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7076495f197732725456992c9a02aed9966139a;p=yosys.git kernel/mem: Add a check() function. --- diff --git a/kernel/mem.cc b/kernel/mem.cc index 9d68dbbb7..7d20833e5 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -52,6 +52,7 @@ void Mem::remove() { } void Mem::emit() { + check(); std::vector rd_left; for (int i = 0; i < GetSize(rd_ports); i++) { auto &port = rd_ports[i]; @@ -257,6 +258,27 @@ Const Mem::get_init_data() const { return init_data; } +void Mem::check() { + for (auto &port : rd_ports) { + if (port.removed) + continue; + log_assert(GetSize(port.clk) == 1); + log_assert(GetSize(port.en) == 1); + log_assert(GetSize(port.data) == width); + if (!port.clk_enable) { + log_assert(!port.transparent); + } + } + for (int i = 0; i < GetSize(wr_ports); i++) { + auto &port = wr_ports[i]; + if (port.removed) + continue; + log_assert(GetSize(port.clk) == 1); + log_assert(GetSize(port.en) == width); + log_assert(GetSize(port.data) == width); + } +} + namespace { struct MemIndex { @@ -333,6 +355,7 @@ namespace { for (auto &it : inits) res.inits.push_back(it.second); } + res.check(); return res; } @@ -389,6 +412,7 @@ namespace { mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, res.width); res.wr_ports.push_back(mwr); } + res.check(); return res; } @@ -451,6 +475,7 @@ Cell *Mem::extract_rdff(int idx) { port.clk = State::S0; port.clk_enable = false; port.clk_polarity = true; + port.transparent = false; return c; } diff --git a/kernel/mem.h b/kernel/mem.h index 547386f3c..f5c7b641f 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -66,6 +66,7 @@ struct Mem { void remove(); void emit(); void clear_inits(); + void check(); Const get_init_data() const; static std::vector get_all_memories(Module *module); static std::vector get_selected_memories(Module *module);