From: lkcl <lkcl@web>
Date: Wed, 29 Jun 2022 10:47:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1468
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c71948e1c79a91db4db5cf067d2e35b30ec4c128;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 9f37c0198..4ac2f68f2 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -90,6 +90,8 @@ The fundamentals are (just like x86 "REP"):
 * Once the loop is completed *only then* is the Program Counter
   allowed to move to the next instruction.
 
+[[!img "svp64-primer/img/power_pipelines.svg" ]]
+
 Hardware (and simulator) implementors are free and clear to implement this
 as literally a for-loop, sitting in between instruction decode and issue.
 Higher performance systems may deploy SIMD backends, multi-issue and