From: lkcl <lkcl@web>
Date: Thu, 26 Nov 2020 23:10:27 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1648
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7337fd92344aaae3552f2402eabff7331cf121e;p=libreriscv.git

---

diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn
index 2e99da05b..d50c8a8ef 100644
--- a/openpower/sv/major_opcode_allocation.mdwn
+++ b/openpower/sv/major_opcode_allocation.mdwn
@@ -26,7 +26,7 @@ likewise switch into the same.
 VBLOCK can be added later by using further VSX dedicated major opcodes
 (EXT62, EXT60)
 
-* EXT00 - unused
+* EXT00 - unused (one instruction: attn)
 * EXT01 - v3.1B prefix
 * EXT02 - twi
 * EXT03 - tdi
@@ -35,6 +35,7 @@ VBLOCK can be added later by using further VSX dedicated major opcodes
 * EXT06 - vector
 * EXT07 - mulli
 * EXT09 - reserved
+* EXT17 - unused (2 instructions: sc, scv)
 * EXT22 - reserved sandbox
 * EXT56 - lq
 * EXT57 - vector ld
@@ -54,6 +55,12 @@ Potential allocations:
 * EXT56/57 - SV-C32-Swizzle
 * EXT60/62 - VBLOCK
 
+Spare: 
+
+* EXT09
+* EXT17
+* EXT22
+
 # Major opcode map
 
 Table 9: Primary Opcode Map (opcode bits 0:5)