From: lkcl Date: Thu, 13 May 2021 16:02:52 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~924 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c73538f465145f2e925d2578c63ef1ea1e01b3be;p=libreriscv.git --- diff --git a/conferences/ics2021.mdwn b/conferences/ics2021.mdwn index d611b9014..84d8f6f11 100644 --- a/conferences/ics2021.mdwn +++ b/conferences/ics2021.mdwn @@ -17,7 +17,7 @@ Project: an entirely Libre-Licensed 3D Hybrid CPU-VPU-GPU based on OpenPOWER. He writes poetry and has been developing a HEP Physics theory for the past 36 years in his spare time. -# SVP64 Abstract +## SVP64 Abstract The OpenPOWER ISA has a strong multi-decades pedigree in Supercomputing: Matrix Multiply, 128-bit SIMD, BCD, Decimal Floating-point have been part @@ -47,7 +47,7 @@ Twin-Predication and "Post-result" predication, and how these will benefit Supercomputing performance and decrease power consumption, by reducing I-Cache usage. -# Comprehensive life-cycle of mixed testing: HDL to gates +## Comprehensive life-cycle of mixed testing: HDL to gates The Libre-SOC Project is developed by Software Engineers with a Hardware background: in particular, Software Engineers with decades of experience @@ -77,3 +77,27 @@ At each and every stage - both pre and post layout and on FPGA - it has been possible to run the exact same JTAG Boundary Scan and basic startup procedure. + +# Jean-Paul Chaput bio + +Jean-Paul Chaput holds a Master Degree in MicroElectronics and Software +Engineering. He joined the LIP6 laboratory within Sorbonne Université or SU +(formerly UPMC) in 2000. Currently he is a Research Engineer in the Analog and +Mixed Signal Team at LIP6. His main focus is on physical level design +software. He is a key contributor in developing and maintaining the +Alliance/Coriolis VLSI CAD projects for CMOS technologies. In particular he +contributed in developing the routers of both Alliance/Coriolis and the whole +Coriolis toolchain infrastructure. He his now a key contributor in extending +Alliance/Coriolis to the Analog Mixed-Signal integration for nanometric CMOS +technologies. + + +## ICS 2021 Abstract + +Starting in 1990, Sorbonne Université-CNRS/LIP6 developed Alliance, a complete +VLSI CAD toolchain released under GPL. In this spirit, we are assembling an +upgraded design flow for ASICs based on FOSS tools like GHDL & Yosys for +logical synthesis and Coriolis2 for physical design. We will present the flow +with a focus on the Coriolis2 part and the LibreSOC first prototype. This +should be an important milestone toward the creation of an open hardware +community.