From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Aug 2022 09:45:44 +0000 (+0100)
Subject: Revert "support assembling svp64 instructions with custom suffixes, like sv.maxu"
X-Git-Tag: sv_maxu_works-initial~71
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c748f032858eb03bd08dc1fa95f2f4912d4b2357;p=openpower-isa.git

Revert "support assembling svp64 instructions with custom suffixes, like sv.maxu"

This reverts commit 0e80cab3b809d432354ca05464e95dc53db11b64.

"sv.ffmadds." is inserted as a 32-bit operation instead of as a ".long"
"sv.ffmadds" on the other hand is correctly converted to ".long"
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 4ae283e9..1e15c799 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1257,8 +1257,6 @@ class SVP64Asm:
         rc = '.' if rc_mode else ''
         yield ".long 0x%08x # %s" % (svp64_prefix.insn.value, insn)
         log(v30b_op, v30b_newfields)
-        if not v30b_op.endswith('.'):
-            v30b_op += rc
         # argh, sv.fmadds etc. need to be done manually
         if v30b_op == 'ffmadds':
             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
@@ -1312,12 +1310,9 @@ class SVP64Asm:
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
             log("fcoss", bin(insn))
             yield ".long 0x%x" % insn
-        elif v30b_op in CUSTOM_INSNS:
-            fields = tuple(map(to_number, v30b_newfields))
-            insn_num = CUSTOM_INSNS[v30b_op](fields)
-            fields_str = ', '.join(v30b_newfields)
-            yield f".long 0x{insn_num:X} # {v30b_op} {fields_str}"
         else:
+            if not v30b_op.endswith('.'):
+                v30b_op += rc
             yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
         log("new v3.0B fields", v30b_op, v30b_newfields)