From: lkcl <lkcl@web>
Date: Sun, 4 Jun 2023 17:03:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c75a503f23c2d8967ac9eb4648a40ab05216d2a9;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010/trial_addi.mdwn b/openpower/sv/rfc/ls010/trial_addi.mdwn
index e5a19d870..e76a79945 100644
--- a/openpower/sv/rfc/ls010/trial_addi.mdwn
+++ b/openpower/sv/rfc/ls010/trial_addi.mdwn
@@ -4,6 +4,14 @@
 Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
 <!-- show -->
 
+The idea here is to review a modified version of a Power ISA 3
+instruction definition, to add SVP64 in a completely non-disruptive
+fashion.
+
+
+
+# SVP64-annotated addi instruction (prototype)
+
 **Add Immediate** D-Form
 
 * addi RT,RA,SI
@@ -38,7 +46,7 @@ Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
 
 **Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
 
-* sv.addi RT,RA,SI 
+* sv.addi RT,RA,SI   (Vectorised on *RT and *RA)
 
 ```
     Prefix: