From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 20:37:57 +0000 (-0800)
Subject: Missing endmodule
X-Git-Tag: working-ls180~881^2^2~157
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c761fa49b73e9ad3680b05e89442adb6fb22b543;p=yosys.git

Missing endmodule
---

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 596a52501..6bdd3bc32 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -288,3 +288,4 @@ endmodule
 module abc9_test033(input clk, d, output reg q1, q2);
 always @(posedge clk) q1 <= d;
 always @(posedge clk) q2 <= q1;
+endmodule