From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 16 Feb 2006 17:03:44 +0000 (-0500)
Subject: Merge ktlim@zizzer:/bk/m5
X-Git-Tag: m5_2.0_beta1~87^2~89^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7624c26e71c1edc73a076efe472d253b199c3cc;p=gem5.git

Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new

arch/alpha/isa/mem.isa:
    Hand merge.

--HG--
extra : convert_revision : c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
---

c7624c26e71c1edc73a076efe472d253b199c3cc
diff --cc arch/alpha/isa/mem.isa
index 0b79bc376,37d0dcf14..df26a534d
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@@ -287,8 -287,7 +287,7 @@@ def template LoadInitiateAcc {
                                        Trace::InstRecord *traceData) const
      {
          Addr EA;
 -        Fault fault = No_Fault;
 +        Fault * fault = NoFault;
-         %(mem_acc_type)s Mem = 0;
  
          %(fp_enable_check)s;
          %(op_src_decl)s;
@@@ -309,10 -308,10 +308,10 @@@ def template LoadCompleteAcc {
                                        %(CPU_exec_context)s *xc,
                                        Trace::InstRecord *traceData) const
      {
 -        Fault fault = No_Fault;
 +        Fault * fault = NoFault;
-         %(mem_acc_type)s Mem = 0;
  
          %(fp_enable_check)s;
+         %(op_src_decl)s;
          %(op_dest_decl)s;
  
          memcpy(&Mem, data, sizeof(Mem));
@@@ -407,9 -406,8 +406,8 @@@ def template StoreInitiateAcc {
                                        Trace::InstRecord *traceData) const
      {
          Addr EA;
 -        Fault fault = No_Fault;
 +        Fault * fault = NoFault;
          uint64_t write_result = 0;
-         %(mem_acc_type)s Mem = 0;
  
          %(fp_enable_check)s;
          %(op_src_decl)s;
@@@ -498,22 -497,12 +497,11 @@@ def template MiscExecute {
  }};
  
  def template MiscInitiateAcc {{
 -    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 +    Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                        Trace::InstRecord *traceData) const
      {
-         Addr EA;
-         Fault * fault = NoFault;
- 
-         %(fp_enable_check)s;
-         %(op_decl)s;
-         %(op_rd)s;
-         %(ea_code)s;
- 
-         if (fault == NoFault) {
-             %(memacc_code)s;
-         }
- 
+         panic("Misc instruction does not support split access method!");
 -
 -        return No_Fault;
 +        return NoFault;
      }
  }};
  
@@@ -523,7 -512,9 +511,9 @@@ def template MiscCompleteAcc {
                                        %(CPU_exec_context)s *xc,
                                        Trace::InstRecord *traceData) const
      {
+         panic("Misc instruction does not support split access method!");
+ 
 -        return No_Fault;
 +        return NoFault;
      }
  }};