From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 22:08:49 +0000 (-0700)
Subject: Fix last_cell.D
X-Git-Tag: working-ls180~1085^2~35
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c76261878340bc87fc5ab2f5ac8c7a1fb5a1b3a2;p=yosys.git

Fix last_cell.D
---

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index ef3e61661..c0c827a25 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -141,8 +141,7 @@ void run_variable(xilinx_srl_pm &pm)
 	if (c->type.in(ID($dff), ID($dffe))) {
 		auto &Q = last_cell->connections_.at(ID(Q));
 		Q = Q[last_slice];
-		auto &D = first_cell->connections_.at(ID(D));
-		D = D[first_slice];
+		last_cell->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
 	}
 
 	if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {