From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 7 Dec 2019 00:23:09 +0000 (-0800)
Subject: Remove creation of $abc9_control_wire
X-Git-Tag: working-ls180~881^2^2~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c767525441ebc6a21b29bf0c1208049cd38adc8e;p=yosys.git

Remove creation of $abc9_control_wire
---

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d5d5a89f6..49000ea25 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -65,15 +65,14 @@
 // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
 //     capture asynchronous behaviour
 // (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
-//     domain (used when partitioning the module so that `abc9' only
+//     domain and polarity (used when partitioning the module so that `abc9' only
 //     performs sequential synthesis (with reachability analysis) correctly on
-//     one domain at a time) and used to infert the delay target
-// (d) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
-//     domain (which, combined with this cell type, encodes to `abc9' which
-//     flops may be merged together)
-// (e) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+//     one domain at a time) and also used to infer the optional delay target
+//     from the (* abc9_clock_period = %d *) attribute attached to any wire
+//     within
+// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
 //     state
-// (f) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 //
 // In order to perform sequential synthesis, `abc9' also requires that
@@ -112,7 +111,6 @@ module FDRE (output Q, input C, CE, D, R);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -140,7 +138,6 @@ module FDRE_1 (output Q, input C, CE, D, R);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -190,7 +187,6 @@ module FDCE (output Q, input C, CE, D, CLR);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -228,7 +224,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -276,7 +271,6 @@ module FDPE (output Q, input C, CE, D, PRE);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -314,8 +308,6 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
->>>>>>> d3b23690... abc9 to use mergeability class to differentiate sync/async
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -352,7 +344,6 @@ module FDSE (output Q, input C, CE, D, S);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -379,7 +370,6 @@ module FDSE_1 (output Q, input C, CE, D, S);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule