From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Oct 2020 14:48:17 +0000 (+0100)
Subject: move LDSTException to mem_types
X-Git-Tag: 24jan2021_ls180~212
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c770cb36585c4e1458f897846d15dfbc55e18de3;p=soc.git

move LDSTException to mem_types
---

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index d766fb90..2d730858 100644
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -6,6 +6,19 @@ based on Anton Blanchard microwatt common.vhdl
 from nmutil.iocontrol import RecordObject
 from nmigen import Signal
 
+# https://bugs.libre-soc.org/show_bug.cgi?id=465
+class LDSTException(RecordObject):
+    def __init__(self, name=None):
+        RecordObject.__init__(self, name=name)
+        self.happened = Signal()
+        self.alignment = Signal()
+        self.instr_fault = Signal()
+        self.invalid = Signal()
+        self.badtree = Signal()
+        self.perm_error = Signal()
+        self.rc_error = Signal()
+        self.segment_fault = Signal()
+
 
 class DCacheToLoadStore1Type(RecordObject):
     def __init__(self, name=None):
diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index dc846c12..2f089c91 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -25,26 +25,14 @@ from nmutil.latch import SRLatch, latchregister
 from nmutil.util import rising_edge
 from soc.decoder.power_decoder2 import Data
 from soc.scoreboard.addr_match import LenExpand
+from soc.experiment.mem_types import LDSTException
 
 # for testing purposes
 from soc.experiment.testmem import TestMemory
 #from soc.scoreboard.addr_split import LDSTSplitter
 
-
 import unittest
 
-class LDSTException(RecordObject):
-    def __init__(self, name=None):
-        RecordObject.__init__(self, name=name)
-        self.happened = Signal()
-        self.alignment = Signal()
-        self.instr_fault = Signal()
-        self.invalid = Signal()
-        self.badtree = Signal()
-        self.perm_error = Signal()
-        self.rc_error = Signal()
-        self.segment_fault = Signal()
-
 
 class PortInterface(RecordObject):
     """PortInterface