From: Anthony Green <green@moxielogic.com>
Date: Fri, 12 Dec 2014 13:44:19 +0000 (-0500)
Subject: Add zex instruction support for moxie port
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c784b1150407a85946f9d45553893349de45a577;p=binutils-gdb.git

Add zex instruction support for moxie port
---

diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index f168fc68316..d3331c6f13f 100644
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,7 @@
+2014-12-12  Anthony Green  <green@moxielogic.com>
+
+	* interp.c (sim_resume): Add zex instructions.
+
 2014-08-19  Alan Modra  <amodra@gmail.com>
 
 	* configure: Regenerate.
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 4362c66bb54..fdb652850e3 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -604,8 +604,24 @@ sim_resume (sd, step, siggnal)
 		cpu.asregs.regs[a] = (int) bv;
 	      }
 	      break;
-	    case 0x12: /* bad */
-	    case 0x13: /* bad */
+	    case 0x12: /* zex.b */
+	      {
+		int a = (inst >> 4) & 0xf;
+		int b = inst & 0xf;
+		signed char bv = cpu.asregs.regs[b];
+		TRACE("zex.b");
+		cpu.asregs.regs[a] = (int) bv & 0xff;
+	      }
+	      break;
+	    case 0x13: /* zex.s */
+	      {
+		int a = (inst >> 4) & 0xf;
+		int b = inst & 0xf;
+		signed short bv = cpu.asregs.regs[b];
+		TRACE("zex.s");
+		cpu.asregs.regs[a] = (int) bv & 0xffff;
+	      }
+	      break;
 	    case 0x14: /* bad */
 	    case 0x15: /* bad */
 	    case 0x16: /* bad */