From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 02:18:05 +0000 (-0700)
Subject: opt_expr to trim A port of $shiftx if Y_WIDTH == 1
X-Git-Tag: working-ls180~1085^2~71
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7859531c2cf56df67a0767a6333ecf9acab7251;p=yosys.git

opt_expr to trim A port of $shiftx if Y_WIDTH == 1
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 858b3560c..b56ce252f 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -745,6 +745,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
+		if (cell->type == ID($shiftx) && cell->getPort(ID::Y).size() == 1) {
+			SigSpec sig_a = assign_map(cell->getPort(ID::A));
+			int width;
+			for (width = GetSize(sig_a); width > 1; width--) {
+				if (sig_a[width-1] != State::Sx)
+					break;
+			}
+
+			if (width < GetSize(sig_a)) {
+				sig_a.remove(width, GetSize(sig_a)-width);
+				cell->setPort(ID::A, sig_a);
+				cell->setParam(ID(A_WIDTH), width);
+				did_something = true;
+				goto next_cell;
+			}
+		}
+
 		if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 &&
 				invert_map.count(assign_map(cell->getPort(ID::A))) != 0) {
 			cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());