From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 18 Apr 2018 04:59:54 +0000 (+0100)
Subject: add RVV exceptions links
X-Git-Tag: convert-csv-opcode-to-binary~5620
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7918072b8fe9e4f7128f17066b27875264688c5;p=libreriscv.git

add RVV exceptions links
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 6599f930b..b94018202 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1341,4 +1341,7 @@ by *introducing* deliberate latency into the execution phase.
 * Fast context save/restore proposal <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/57F823FA.6030701%40gmail.com>
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Expired Patent on Vector Virtual Memory solutions
-  <https://patentimages.storage.googleapis.com/fc/f6/e2/2cbee92fcd8743/US5895501.pdf?
+  <https://patentimages.storage.googleapis.com/fc/f6/e2/2cbee92fcd8743/US5895501.pdf>
+* Discussion on RVV "re-entrant" capabilities allowing operations to be
+  restarted if an exception occurs (VM page-table miss)
+  <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IuNFitTw9fM/CCKBUlzsAAAJ>