From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 23:53:22 +0000 (+0200)
Subject: Fixed bug in "read_verilog -ignore_redef"
X-Git-Tag: yosys-0.4~259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7afbd9d8efcf3045d9e4244600ce8d8e0d40b6d;p=yosys.git

Fixed bug in "read_verilog -ignore_redef"
---

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 551859ebf..ec9616be3 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -947,7 +947,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			if (!ignore_redef)
 				log_error("Re-definition of module `%s' at %s:%d!\n",
 						(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
-			log_error("Ignoring re-definition of module `%s' at %s:%d!\n",
+			log("Ignoring re-definition of module `%s' at %s:%d!\n",
 					(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 			continue;
 		}