From: Luke Kenneth Casson Leighton Date: Wed, 27 Mar 2019 11:06:08 +0000 (+0000) Subject: add RecordBasedStage, PassThroughStage and RegisterPipeline classes X-Git-Tag: ls180-24jan2020~1474 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7b2626f89f9c419f14e88e7f87490bf14b88659;p=ieee754fpu.git add RecordBasedStage, PassThroughStage and RegisterPipeline classes --- diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 38175dd2..c13d1999 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -255,6 +255,20 @@ class Stage(metaclass=ABCMeta): def process(i): pass +class RecordBasedStage(Stage): + """ convenience class which provides a Records-based layout. + """ +   def __init__(self, in_shape, out_shape, processfn, setupfn=None): +      self.in_shape = in_shape +      self.out_shape = out_shape +      self.__process = processfn +      self.__setup = setupfn +   def ispec(self): return Record(self.in_shape) +   def ospec(self): return Record(self.out_shape) +   def process(seif, i): return self.__process(i) +   def setup(seif, m, i): return self.__setup(m, i) + + class StageChain(StageCls): """ pass in a list of stages, and they will automatically be chained together via their input and output specs into a @@ -547,3 +561,23 @@ class UnbufferedPipeline(ControlBase): m.d.comb += eq(self.n.o_data, result) return m + +class PassThroughStage(StageCls): + """ a pass-through stage which has its input data spec equal to its output, + and "passes through" its data from input to output. + """ + def __init__(self, iospec): + self.iospecfn = iospecfn + def ispec(self): return self.iospecfn() + def ospec(self): return self.iospecfn() + def process(self, i): return i + + +class RegisterPipeline(UnbufferedPipeline): + """ A pipeline stage that delays by one clock cycle, creating a + sync'd latch out of o_data and o_valid as an indirect byproduct + of using PassThroughStage + """ + def __init__(self, iospecfn): + UnbufferedPipeline.__init__(self, PassThroughStage(iospecfn)) +