From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 11:03:30 +0000 (+0100)
Subject: add vector demo set inc first
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7b41ac1f363b48a241252f1aacc1603e60cf95e;p=libreriscv.git

add vector demo set inc first
---

diff --git a/openpower/sv/sif.py b/openpower/sv/sif.py
new file mode 100644
index 000000000..9f2455f2e
--- /dev/null
+++ b/openpower/sv/sif.py
@@ -0,0 +1,34 @@
+def sif(RA, mask=None):
+    RT = RA if mask is not None else 0
+    i = 0
+    # start setting if no predicate or if 1st predicate bit set
+    setting_mode = mask is None
+    while i < 16:
+        bit = 1<<i
+        if not setting_mode and mask is not None and (mask & bit):
+            setting_mode = True # back into "setting" mode
+        if setting_mode:
+            if RA & bit: # found a bit in rs1: stop setting RT
+                setting_mode = False
+            RT |= bit
+        i += 1
+    return RT
+
+if __name__ == '__main__':
+     m  = 0b11000011
+     v3 = 0b10010100 # vmsif.m v2, v3
+     v2 = 0b11000011 # v2
+     RT = sif(v3, m)
+     print(bin(v3), bin(v2), bin(RT))
+     v3 = 0b10010100 # vmsif.m v2, v3
+     v2 = 0b00000111 # v2 contents
+     RT = sif(v3)
+     print(bin(v3), bin(v2), bin(RT))
+     v3 = 0b10010101 # vmsif.m v2, v3
+     v2 = 0b00000000 # v2
+     RT = sif(v3)
+     print(bin(v3), bin(v2), bin(RT))
+     v3 = 0b00000000 # vmsif.m v2, v3
+     v2 = 0b11111111 # v2
+     RT = sif(v3)
+     print(bin(v3), bin(v2), bin(RT))