From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 29 Feb 2020 19:46:57 +0000 (-0500)
Subject: Add input and output register selector fields
X-Git-Tag: div_pipeline~1812
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7bc5a0359afd57cef98ce660f0da744bdd7defc;p=soc.git

Add input and output register selector fields
---

diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py
index 5bab5537..0e0f1f22 100644
--- a/src/decoder/power_major_decoder.py
+++ b/src/decoder/power_major_decoder.py
@@ -26,6 +26,41 @@ class InternalOp(Enum):
     OP_XOR = 11
 
 
+@unique
+class In1Sel(Enum):
+    RA = 0
+    RA_OR_ZERO = 1
+    NONE = 2
+    SPR = 3
+
+
+@unique
+class In2Sel(Enum):
+    CONST_SI = 0
+    CONST_SI_HI = 1
+    CONST_UI = 2
+    CONST_UI_HI = 3
+    CONST_LI = 4
+    CONST_BD = 5
+    CONST_SH32 = 6
+    RB = 7
+
+
+@unique
+class In3Sel(Enum):
+    NONE = 0
+    RS = 1
+
+
+@unique
+class OutSel(Enum):
+    RT = 0
+    RA = 1
+    NONE = 2
+    SPR = 3
+
+
+
 def get_csv(name):
     file_dir = os.path.dirname(os.path.realpath(__file__))
     with open(os.path.join(file_dir, name)) as csvfile:
@@ -42,6 +77,10 @@ class PowerMajorDecoder(Elaboratable):
 
         self.function_unit = Signal(Function, reset_less=True)
         self.internal_op = Signal(InternalOp, reset_less=True)
+        self.in1_sel = Signal(In1Sel, reset_less=True)
+        self.in2_sel = Signal(In2Sel, reset_less=True)
+        self.in3_sel = Signal(In3Sel, reset_less=True)
+        self.out_sel = Signal(OutSel, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -53,9 +92,17 @@ class PowerMajorDecoder(Elaboratable):
                 with m.Case(opcode):
                     comb += self.function_unit.eq(Function[row['unit']])
                     comb += self.internal_op.eq(InternalOp[row['internal op']])
+                    comb += self.in1_sel.eq(In1Sel[row['in1']])
+                    comb += self.in2_sel.eq(In2Sel[row['in2']])
+                    comb += self.in3_sel.eq(In3Sel[row['in3']])
+                    comb += self.out_sel.eq(OutSel[row['out']])
         return m
 
     def ports(self):
         return [self.opcode_in,
                 self.function_unit,
+                self.in1_sel,
+                self.in2_sel,
+                self.in3_sel,
+                self.out_sel,
                 self.internal_op]
diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index 321772eb..bfffd7cf 100644
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -6,6 +6,7 @@ import sys
 import unittest
 sys.path.append("../")
 from power_major_decoder import (PowerMajorDecoder, Function,
+                                 In1Sel, In2Sel, In3Sel, OutSel,
                                  InternalOp, major_opcodes)
 
 
@@ -16,10 +17,18 @@ class DecoderTestCase(FHDLTestCase):
         opcode = Signal(6)
         function_unit = Signal(Function)
         internal_op = Signal(InternalOp)
+        in1_sel = Signal(In1Sel)
+        in2_sel = Signal(In2Sel)
+        in3_sel = Signal(In3Sel)
+        out_sel = Signal(OutSel)
 
         m.submodules.dut = dut = PowerMajorDecoder()
         comb += [dut.opcode_in.eq(opcode),
                  function_unit.eq(dut.function_unit),
+                 in1_sel.eq(dut.in1_sel),
+                 in2_sel.eq(dut.in2_sel),
+                 in3_sel.eq(dut.in3_sel),
+                 out_sel.eq(dut.out_sel),
                  internal_op.eq(dut.internal_op)]
 
         sim = Simulator(m)
@@ -35,9 +44,26 @@ class DecoderTestCase(FHDLTestCase):
                 result = yield internal_op
                 expected = InternalOp[row['internal op']].value
                 self.assertEqual(expected, result)
+
+                result = yield in1_sel
+                expected = In1Sel[row['in1']].value
+                self.assertEqual(expected, result)
+
+                result = yield in2_sel
+                expected = In2Sel[row['in2']].value
+                self.assertEqual(expected, result)
+
+                result = yield in3_sel
+                expected = In3Sel[row['in3']].value
+                self.assertEqual(expected, result)
+
+                result = yield out_sel
+                expected = OutSel[row['out']].value
+                self.assertEqual(expected, result)
         sim.add_process(process)
         with sim.write_vcd("test.vcd", "test.gtkw", traces=[
-                opcode, function_unit, internal_op]):
+                opcode, function_unit, internal_op,
+                in1_sel, in2_sel]):
             sim.run()
 
     def test_ilang(self):