From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Jul 2020 21:08:15 +0000 (+0100)
Subject: debug information related to 32/64 bit mode
X-Git-Tag: div_pipeline~121
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7bda92aca2a980262b6ac3f8f6249e3521edfbb;p=soc.git

debug information related to 32/64 bit mode
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index a2c2028d..bf78fb19 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -3,6 +3,10 @@
 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
 not speed, it is for both learning and educational purposes, as well as
 a method of verifying the HDL.
+
+related bugs:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=424
 """
 
 from functools import wraps
@@ -446,11 +450,19 @@ class ISACaller:
 
     def handle_comparison(self, outputs):
         out = outputs[0]
+        print ("handle_comparison", out.bits, hex(out.value))
+        # TODO - XXX *processor* in 32-bit mode
+        # https://bugs.libre-soc.org/show_bug.cgi?id=424
+        #if is_32bit:
+        #    o32 = exts(out.value, 32)
+        #    print ("handle_comparison exts 32 bit", hex(o32))
         out = exts(out.value, out.bits)
+        print ("handle_comparison exts", hex(out))
         zero = SelectableInt(out == 0, 1)
         positive = SelectableInt(out > 0, 1)
         negative = SelectableInt(out < 0, 1)
         SO = self.spr['XER'][XER_bits['SO']]
+        print ("handle_comparison SO", SO)
         cr_field = selectconcat(negative, positive, zero, SO)
         self.crl[0].eq(cr_field)