From: Kristian H. Kristensen <hoegsberg@chromium.org>
Date: Mon, 25 Mar 2019 21:04:20 +0000 (-0700)
Subject: freedreno/ir3: Fix operand order for DSX/DSY
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7c432738a68d543dc1b73eae895ec4dfacd92b2;p=mesa.git

freedreno/ir3: Fix operand order for DSX/DSY

Most cat5 instructions are constructed using ir3_SAM, which uses
regs[1] for the (sampler, tex) src. Not DSX/DSY though, so we look up
src1 and src2 differently for those two.

Fixes: 1dffb089 ("freedreno/ir3: fix sam.s2en encoding")
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
---

diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c
index 23b12a6fc5f..f209585dd9a 100644
--- a/src/freedreno/ir3/ir3.c
+++ b/src/freedreno/ir3/ir3.c
@@ -455,6 +455,21 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
 	struct ir3_register *src2 = instr->regs[3];
 	instr_cat5_t *cat5 = ptr;
 
+	switch (instr->opc) {
+	case OPC_DSX:
+	case OPC_DSXPP_1:
+	case OPC_DSY:
+	case OPC_DSYPP_1:
+		iassert((instr->flags & IR3_INSTR_S2EN) == 0);
+		src1 = instr->regs[1];
+		src2 = instr->regs[2];
+		break;
+	default:
+		src1 = instr->regs[2];
+		src2 = instr->regs[3];
+		break;
+	}
+
 	iassert_type(dst, type_size(instr->cat5.type) == 32)
 
 	assume(src1 || !src2);