From: lkcl <lkcl@web>
Date: Sun, 12 Sep 2021 10:55:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7db4d89462eff744d8dd67e1b1abbd160def110;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 1a6e6f6c5..439392b2d 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -90,8 +90,8 @@ which may be enabled and combined):
 * **VLSET Mode**: identical to Data-Dependent Fail-First Mode
   for Arithmetic SVP64 operations, with more
   flexibility and a close interaction and integration into the
-  underlying base Scalar v3.0B Branch instruction, truncating
-  VL at the early-exit point.
+  underlying base Scalar v3.0B Branch instruction.
+  Truncation of VL takes place around the early-exit point.
 * **CTR-test Mode**: gives much more flexibility over when and why
   CTR is decremented, including options to decrement if a Condition
   test succeeds *or if it fails*.