From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 13 May 2014 15:45:15 +0000 (+0200)
Subject: sim: fix tb_trigger_csr
X-Git-Tag: 24jan2021_ls180~2575^2~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7e100f93bd72307cf92436a9e5e3379077a0cf1;p=litex.git

sim: fix tb_trigger_csr
---

diff --git a/sim/tb_trigger_csr.py b/sim/tb_trigger_csr.py
index 28cf7e1b..bc796ed8 100644
--- a/sim/tb_trigger_csr.py
+++ b/sim/tb_trigger_csr.py
@@ -27,10 +27,11 @@ def csr_prog_mila(bus, regs):
 	regs.trigger_port0_mask.write(0xFFFFFFFF)
 	regs.trigger_port0_trig.write(0xDEADBEEF)
 	regs.trigger_port1_mask.write(0xFFFFFFFF)
-	regs.trigger_port1_trig.write(0xDEADBEEF)
-	regs.trigger_port1_mask.write(0xFFFFFFFF)
-	regs.trigger_port1_mask.write(0xFFFFFFFF)
-	regs.trigger_port1_trig.write(0xDEADBEEF)
+	regs.trigger_port1_trig.write(0xCAFEFADE)
+	regs.trigger_port2_mask.write(0xFFFFFFFF)
+	regs.trigger_port2_trig.write(0xDEADBEEF)
+	regs.trigger_port3_mask.write(0xFFFFFFFF)
+	regs.trigger_port3_trig.write(0xCAFEFADE)
 
 	sum_tt = gen_truth_table("i1 & i2 & i3 & i4")
 	sum_trans = []
@@ -91,7 +92,6 @@ class TB(Module):
 			selfp.terms[1].sink.dat = 0xCAFEFADE
 			selfp.terms[2].sink.dat = 0xDEADBEEF
 			selfp.terms[3].sink.dat = 0xCAFEFADE
-		raise StopSimulation
 
 def main():
 	tb = TB(addrmap="csr.csv")