From: lkcl <lkcl@web>
Date: Mon, 4 Jul 2022 13:21:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1348
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7e4440733ace9d8ea8b65b7a3254be555409a2a;p=libreriscv.git

---

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 0b8f47c1d..2e1e54466 100644
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -31,13 +31,16 @@ FP instructions: useful for testing <http://weitz.de/ieee/>
 * [[isa/fparith]]
 * [[isa/fpcvt]]
 
-Variants only available under the [[sv/svp64]] namespace, these are
-all **DRAFT FORM**. Explanation of the rules for twin register targets
+Scalar instructions added as part of [[sv/svp64]] development, these are
+all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
+on Simple-V).
+Explanation of the rules for twin register targets
 (implicit RS, FRS) explained in SVPY4 [[sv/svp64/appendix]]
 
-* [[isa/svfixedload]]
+* [[isa/svfixedload]] DEPRECATED, do not use.
 * [[isa/svfixedarith]]
 * [[isa/svfparith]]
+* [[isa/bitmanip]]
 
 Part of the DRAFT Simple-V Specification: