From: lkcl <lkcl@web>
Date: Thu, 23 Nov 2023 17:29:42 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7ef90712d7b07998ca33d2e19cd50cad45a3c72;p=libreriscv.git

---

diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn
index f0f60e36a..3a49b10ea 100644
--- a/nlnet_2023_simplev_riscv.mdwn
+++ b/nlnet_2023_simplev_riscv.mdwn
@@ -74,7 +74,6 @@ Key phases of this project are:
 * Documentation, demonstrations and Conference Papers. This will include porting 
   results of other completed projects (cryptoprimitives, video) from POWER ISA to 
   the RISC-V/Simple-V environment
-
 * Research and assessment of ARM7 and i486 (both on opencores.org) as well as ARC
   as to their feasibility for applying Simple-V Prefixing in future development projects