From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Mon, 25 Sep 2023 17:20:01 +0000 (+0100)
Subject: Added spaces and brackets for lbzux instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7f0bcf9295a3d02f1ac88548c147992302ada39;p=openpower-isa.git

Added spaces and brackets for lbzux instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 3bedcb29..5e704587 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -102,11 +102,15 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
-Description:Let the effective address (EA) be the sum (RA)+ (RB).
-The byte in storage addressed by EA is loaded into
-RT56:63. RT0:55 are set to 0.
-EA is placed into register RA.
-If RA=0 or RA=RT, the instruction form is invalid.
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    The byte in storage addressed by EA is loaded into
+    RT[56:63]. RT[0:55] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: