From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Aug 2014 18:19:50 +0000 (+0200)
Subject: Fixed "share" for memory read ports
X-Git-Tag: yosys-0.4~310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c7f99be3be828606cafc7d35b3612f5344065736;p=yosys.git

Fixed "share" for memory read ports
---

diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 4484d6771..0c88b4d3c 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -419,6 +419,13 @@ struct ShareWorker
 			return supercell;
 		}
 
+		if (c1->type == "$memrd")
+		{
+			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
+			module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA"));
+			return supercell;
+		}
+
 		log_abort();
 	}