From: Chia-I Wu Date: Thu, 8 Oct 2015 08:51:50 +0000 (+0800) Subject: ilo: improve Gen8 defines based on its PRMs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8083b1adc79073c0d6fc3bb87d6a18e41c779c4;p=mesa.git ilo: improve Gen8 defines based on its PRMs --- diff --git a/src/gallium/drivers/ilo/core/ilo_state_cc.c b/src/gallium/drivers/ilo/core/ilo_state_cc.c index 83ee8de979c..1f2456e19ea 100644 --- a/src/gallium/drivers/ilo/core/ilo_state_cc.c +++ b/src/gallium/drivers/ilo/core/ilo_state_cc.c @@ -694,10 +694,10 @@ cc_set_gen8_3DSTATE_PS_BLEND(struct ilo_state_cc *cc, cc_get_gen6_effective_rt(dev, info, 0, &rt0); /* 0x0 is reserved for blend factors and we have to set them all */ - dw1 |= rt0.a_src << GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__SHIFT | - rt0.a_dst << GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__SHIFT | - rt0.rgb_src << GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__SHIFT | - rt0.rgb_dst << GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__SHIFT; + dw1 |= rt0.a_src << GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT | + rt0.a_dst << GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT | + rt0.rgb_src << GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT | + rt0.rgb_dst << GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT; for (i = 0; i < blend->rt_count; i++) { if (blend->rt[i].argb_write_disables != 0xf) { @@ -707,10 +707,10 @@ cc_set_gen8_3DSTATE_PS_BLEND(struct ilo_state_cc *cc, } if (rt0.blend_enable) { - dw1 |= GEN8_PS_BLEND_DW1_BLEND_ENABLE; + dw1 |= GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE; if (rt0.a_src != rt0.rgb_src || rt0.a_dst != rt0.rgb_dst) - dw1 |= GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE; + dw1 |= GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE; } } diff --git a/src/gallium/drivers/ilo/core/ilo_state_raster.c b/src/gallium/drivers/ilo/core/ilo_state_raster.c index ed64a1f0d3c..a694f71bbbf 100644 --- a/src/gallium/drivers/ilo/core/ilo_state_raster.c +++ b/src/gallium/drivers/ilo/core/ilo_state_raster.c @@ -512,7 +512,7 @@ raster_set_gen8_3DSTATE_RASTER(struct ilo_state_raster *rs, /* where should line_msaa_enable be set? */ if (setup->msaa_enable) - dw1 |= GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE; + dw1 |= GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE; if (tri->depth_offset_solid) dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID; @@ -574,10 +574,6 @@ get_gen6_sample_count(const struct ilo_dev *dev, uint8_t sample_count) c = GEN7_NUMSAMPLES_8; min_gen = ILO_GEN(7); break; - case 16: - c = GEN8_NUMSAMPLES_16; - min_gen = ILO_GEN(8); - break; default: assert(!"unexpected sample count"); c = GEN6_NUMSAMPLES_1; @@ -792,17 +788,17 @@ raster_set_gen8_3DSTATE_WM(struct ilo_state_raster *rs, if (ilo_dev_gen(dev) < ILO_GEN(8)) { switch (scan->earlyz_op) { case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR: - dw1 |= GEN7_WM_DW1_DEPTH_CLEAR; + dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_CLEAR; break; case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE: - dw1 |= GEN7_WM_DW1_DEPTH_RESOLVE; + dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE; break; case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE: - dw1 |= GEN7_WM_DW1_HIZ_RESOLVE; + dw1 |= GEN7_WM_DW1_LEGACY_HIZ_RESOLVE; break; default: if (scan->earlyz_stencil_clear) - dw1 |= GEN7_WM_DW1_DEPTH_CLEAR; + dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_CLEAR; break; } } diff --git a/src/gallium/drivers/ilo/core/ilo_state_sbe.c b/src/gallium/drivers/ilo/core/ilo_state_sbe.c index 5d1d400acdd..1b4ca0683c9 100644 --- a/src/gallium/drivers/ilo/core/ilo_state_sbe.c +++ b/src/gallium/drivers/ilo/core/ilo_state_sbe.c @@ -239,8 +239,8 @@ sbe_set_gen8_3DSTATE_SBE(struct ilo_state_sbe *sbe, vue_read_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT; if (ilo_dev_gen(dev) >= ILO_GEN(8)) { - dw1 |= GEN8_SBE_DW1_USE_URB_READ_LEN | - GEN8_SBE_DW1_USE_URB_READ_OFFSET | + dw1 |= GEN8_SBE_DW1_FORCE_URB_READ_LEN | + GEN8_SBE_DW1_FORCE_URB_READ_OFFSET | vue_read_offset << GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT; } else { dw1 |= vue_read_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT; @@ -286,10 +286,10 @@ sbe_set_gen8_3DSTATE_SBE_SWIZ(struct ilo_state_sbe *sbe, swizzle->attr << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT; if (swizzle->force_zeros) { - swiz[i] |= GEN8_SBE_SWIZ_OVERRIDE_W | - GEN8_SBE_SWIZ_OVERRIDE_Z | - GEN8_SBE_SWIZ_OVERRIDE_Y | - GEN8_SBE_SWIZ_OVERRIDE_X | + swiz[i] |= GEN8_SBE_SWIZ_CONST_OVERRIDE_W | + GEN8_SBE_SWIZ_CONST_OVERRIDE_Z | + GEN8_SBE_SWIZ_CONST_OVERRIDE_Y | + GEN8_SBE_SWIZ_CONST_OVERRIDE_X | GEN8_SBE_SWIZ_CONST_0000; } } diff --git a/src/gallium/drivers/ilo/core/ilo_state_surface.c b/src/gallium/drivers/ilo/core/ilo_state_surface.c index 40fe15f316f..27c37535fc8 100644 --- a/src/gallium/drivers/ilo/core/ilo_state_surface.c +++ b/src/gallium/drivers/ilo/core/ilo_state_surface.c @@ -814,10 +814,6 @@ surface_get_gen6_image_sample_count(const struct ilo_dev *dev, *sample_count = GEN7_NUMSAMPLES_8; min_gen = ILO_GEN(7); break; - case 16: - *sample_count = GEN8_NUMSAMPLES_16; - min_gen = ILO_GEN(8); - break; default: assert(!"invalid sample count"); *sample_count = GEN6_NUMSAMPLES_1; diff --git a/src/gallium/drivers/ilo/core/ilo_state_vf.c b/src/gallium/drivers/ilo/core/ilo_state_vf.c index 9faf835fef2..8f091e21a27 100644 --- a/src/gallium/drivers/ilo/core/ilo_state_vf.c +++ b/src/gallium/drivers/ilo/core/ilo_state_vf.c @@ -369,14 +369,14 @@ vf_params_set_gen8_3DSTATE_VF_SGVS(struct ilo_state_vf *vf, if (params->prepend_instanceid) { dw1 |= GEN8_SGVS_DW1_IID_ENABLE | - 1 << GEN8_SGVS_DW1_IID_VE_COMP__SHIFT | - attr << GEN8_SGVS_DW1_IID_VE_INDEX__SHIFT; + 1 << GEN8_SGVS_DW1_IID_COMP__SHIFT | + attr << GEN8_SGVS_DW1_IID_OFFSET__SHIFT; } if (params->prepend_vertexid) { dw1 |= GEN8_SGVS_DW1_VID_ENABLE | - 0 << GEN8_SGVS_DW1_VID_VE_COMP__SHIFT | - attr << GEN8_SGVS_DW1_VID_VE_INDEX__SHIFT; + 0 << GEN8_SGVS_DW1_VID_COMP__SHIFT | + attr << GEN8_SGVS_DW1_VID_OFFSET__SHIFT; } STATIC_ASSERT(ARRAY_SIZE(vf->sgvs) >= 1); diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h index fe8b26908c0..96cf543d27e 100644 --- a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h @@ -41,7 +41,9 @@ enum gen_eu_urb_op { GEN7_MSG_URB_READ_OWORD = 0x3, GEN7_MSG_URB_ATOMIC_MOV = 0x4, GEN7_MSG_URB_ATOMIC_INC = 0x5, + GEN75_MSG_URB_ATOMIC_ADD = 0x6, GEN8_MSG_URB_SIMD8_WRITE = 0x7, + GEN8_MSG_URB_SIMD8_READ = 0x8, }; enum gen_eu_pi_simd { @@ -137,6 +139,7 @@ enum gen_eu_dp_op { GEN75_MSG_DP_RC_MEMORY_FENCE = 0x7, GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE = 0xa, GEN75_MSG_DP_RC_RT_WRITE = 0xc, + GEN8_MSG_DP_RC_RT_READ = 0xd, GEN75_MSG_DP_CC_OWORD_BLOCK_READ = 0x0, GEN75_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ = 0x1, GEN75_MSG_DP_CC_OWORD_DUAL_BLOCK_READ = 0x2, diff --git a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h index 5a0bb4f8d77..36f9618eb2d 100644 --- a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h @@ -84,6 +84,8 @@ enum gen_mi_alu_operand { #define GEN7_MI_OPCODE_MI_PREDICATE (0xc << 23) #define GEN7_MI_OPCODE_MI_URB_CLEAR (0x19 << 23) #define GEN75_MI_OPCODE_MI_MATH (0x1a << 23) +#define GEN8_MI_OPCODE_MI_SEMAPHORE_SIGNAL (0x1b << 23) +#define GEN8_MI_OPCODE_MI_SEMAPHORE_WAIT (0x1c << 23) #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23) #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23) #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23) @@ -91,8 +93,11 @@ enum gen_mi_alu_operand { #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23) #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23) #define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG (0x2a << 23) +#define GEN75_MI_OPCODE_MI_RS_STORE_DATA_IMM (0x2b << 23) #define GEN75_MI_OPCODE_MI_LOAD_URB_MEM (0x2c << 23) #define GEN75_MI_OPCODE_MI_STORE_URB_MEM (0x2d << 23) +#define GEN8_MI_OPCODE_MI_COPY_MEM_MEM (0x2e << 23) +#define GEN8_MI_OPCODE_MI_ATOMIC (0x2f << 23) #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23) #define GEN6_MI_LENGTH__MASK 0x0000003f #define GEN6_MI_LENGTH__SHIFT 0 @@ -155,8 +160,41 @@ enum gen_mi_alu_operand { #define GEN75_MI_MATH_DW_SRC2__MASK 0x000007ff #define GEN75_MI_MATH_DW_SRC2__SHIFT 0 +#define GEN8_MI_SEMAPHORE_SIGNAL__SIZE 2 +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_POST_SYNC_OP (0x1 << 21) +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__MASK 0x00038000 +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__SHIFT 15 +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_RCS (0x0 << 15) +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS0 (0x1 << 15) +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_BCS (0x2 << 15) +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VECS (0x3 << 15) +#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS1 (0x4 << 15) + + +#define GEN8_MI_SEMAPHORE_WAIT__SIZE 4 +#define GEN8_MI_SEMAPHORE_WAIT_DW0_USE_GGTT (0x1 << 22) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__MASK 0x00008000 +#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__SHIFT 15 +#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_SIGNAL (0x0 << 15) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_POLL (0x1 << 15) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__MASK 0x00007000 +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__SHIFT 12 +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_SDD (0x0 << 12) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_OR_EQUAL_SDD (0x1 << 12) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_SDD (0x2 << 12) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_OR_EQUAL_SDD (0x3 << 12) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_EQUAL_SDD (0x4 << 12) +#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_NO_EQUAL_SDD (0x5 << 12) + + +#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__MASK 0xfffffffc +#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHIFT 2 +#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHR 2 + + #define GEN6_MI_STORE_DATA_IMM__SIZE 6 #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22) +#define GEN8_MI_STORE_DATA_IMM_DW0_STORE_QWORD (0x1 << 21) #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc @@ -188,7 +226,17 @@ enum gen_mi_alu_operand { #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2 -#define GEN6_MI_FLUSH_DW__SIZE 4 +#define GEN6_MI_FLUSH_DW__SIZE 5 +#define GEN6_MI_FLUSH_DW_DW0_WRITE__MASK 0x0000c000 +#define GEN6_MI_FLUSH_DW_DW0_WRITE__SHIFT 14 +#define GEN6_MI_FLUSH_DW_DW0_WRITE_NONE (0x0 << 14) +#define GEN6_MI_FLUSH_DW_DW0_WRITE_IMM (0x1 << 14) +#define GEN6_MI_FLUSH_DW_DW0_WRITE_TIMESTAMP (0x3 << 14) + +#define GEN6_MI_FLUSH_DW_DW1_USE_GGTT (0x1 << 2) +#define GEN6_MI_FLUSH_DW_DW1_ADDR__MASK 0xfffffff8 +#define GEN6_MI_FLUSH_DW_DW1_ADDR__SHIFT 3 +#define GEN6_MI_FLUSH_DW_DW1_ADDR__SHR 3 @@ -225,6 +273,17 @@ enum gen_mi_alu_operand { #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT 2 #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR 2 +#define GEN75_MI_RS_STORE_DATA_IMM__SIZE 6 +#define GEN75_MI_RS_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22) + + +#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc +#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHIFT 2 +#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHR 2 + + + + #define GEN75_MI_LOAD_URB_MEM__SIZE 4 #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK 0x00007ffc @@ -247,12 +306,47 @@ enum gen_mi_alu_operand { #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR 6 +#define GEN8_MI_COPY_MEM_MEM__SIZE 5 +#define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_SRC (0x1 << 22) +#define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_DST (0x1 << 21) + +#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__MASK 0xfffffffc +#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHIFT 2 +#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHR 2 + + +#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__MASK 0xfffffffc +#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHIFT 2 +#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHR 2 + + +#define GEN8_MI_ATOMIC__SIZE 11 +#define GEN8_MI_ATOMIC_DW0_USE_GGTT (0x1 << 22) +#define GEN8_MI_ATOMIC_DW0_POST_SYNC_OP (0x1 << 21) +#define GEN8_MI_ATOMIC_DW0_SIZE__MASK 0x00180000 +#define GEN8_MI_ATOMIC_DW0_SIZE__SHIFT 19 +#define GEN8_MI_ATOMIC_DW0_SIZE_DWORD (0x0 << 19) +#define GEN8_MI_ATOMIC_DW0_SIZE_QWORD (0x1 << 19) +#define GEN8_MI_ATOMIC_DW0_SIZE_OWORD (0x2 << 19) +#define GEN8_MI_ATOMIC_DW0_INLINE_DATA (0x1 << 18) +#define GEN8_MI_ATOMIC_DW0_CS_STALL (0x1 << 17) +#define GEN8_MI_ATOMIC_DW0_RETURN_DATA_CONTROL (0x1 << 16) +#define GEN8_MI_ATOMIC_DW0_OP__MASK 0x0000ff00 +#define GEN8_MI_ATOMIC_DW0_OP__SHIFT 8 + +#define GEN8_MI_ATOMIC_DW1_ADDR__MASK 0xfffffffc +#define GEN8_MI_ATOMIC_DW1_ADDR__SHIFT 2 +#define GEN8_MI_ATOMIC_DW1_ADDR__SHR 2 + + + #define GEN6_MI_BATCH_BUFFER_START__SIZE 3 #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22) #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16) #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15) #define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13) #define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11) +#define GEN75_MI_BATCH_BUFFER_START_DW0_RS_ENABLE (0x1 << 10) #define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8) #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc diff --git a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h index c51e4f78bc0..54ec13eaafa 100644 --- a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h @@ -37,6 +37,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_REG__SIZE 0x400000 #define GEN6_REG_NOPID 0x2094 + +#define GEN6_REG_SO_PRIM_STORAGE_NEEDED 0x2280 + +#define GEN6_REG_SO_NUM_PRIMS_WRITTEN 0x2288 + + +#define GEN7_REG_TS_GPGPU_THREADS_DISPATCHED 0x2290 + #define GEN7_REG_HS_INVOCATION_COUNT 0x2300 #define GEN7_REG_DS_INVOCATION_COUNT 0x2308 @@ -95,10 +103,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN75_REG_CS_GPR__ESIZE 0x8 #define GEN75_REG_CS_GPR__LEN 0x10 +#define GEN7_REG_GPGPU_DISPATCHDIMX 0x2500 -#define GEN6_REG_SO_PRIM_STORAGE_NEEDED 0x2280 +#define GEN7_REG_GPGPU_DISPATCHDIMY 0x2504 -#define GEN6_REG_SO_NUM_PRIMS_WRITTEN 0x2288 +#define GEN7_REG_GPGPU_DISPATCHDIMZ 0x2508 #define GEN7_REG_SO_NUM_PRIMS_WRITTEN(i0) (0x5200 + 0x8*(i0)) @@ -118,8 +127,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_REG_CACHE_MODE_0_HIZ_RAW_STALL_OPT_DISABLE (0x1 << 2) #define GEN7_REG_CACHE_MODE_1 0x7004 -#define GEN8_REG_CACHE_MODE_1_HIZ_NP_EARLY_Z_FAILS_DISABLE (0x1 << 13) -#define GEN8_REG_CACHE_MODE_1_HIZ_NP_PMA_FIX_ENABLE (0x1 << 11) +#define GEN8_REG_CACHE_MODE_1_NP_EARLY_Z_FAILS_DISABLE (0x1 << 13) +#define GEN8_REG_CACHE_MODE_1_NP_PMA_FIX_ENABLE (0x1 << 11) #define GEN8_REG_L3CNTLREG 0x7034 diff --git a/src/gallium/drivers/ilo/genhw/gen_render.xml.h b/src/gallium/drivers/ilo/genhw/gen_render.xml.h index 2e86ba96ae2..43d271d838a 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render.xml.h @@ -102,6 +102,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_VS (0x34 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_GS (0x35 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_HS (0x36 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_DS (0x37 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_PS (0x38 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_VS (0x43 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_GS (0x44 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_HS (0x45 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_DS (0x45 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_PS (0x46 << 16) #define GEN8_RENDER_OPCODE_3DSTATE_VF_INSTANCING (0x49 << 16) #define GEN8_RENDER_OPCODE_3DSTATE_VF_SGVS (0x4a << 16) #define GEN8_RENDER_OPCODE_3DSTATE_VF_TOPOLOGY (0x4b << 16) @@ -130,6 +140,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POOL_ALLOC (0x119 << 16) +#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_POOL_ALLOC (0x11a << 16) #define GEN8_RENDER_OPCODE_3DSTATE_SAMPLE_PATTERN (0x11c << 16) #define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16) #define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16) @@ -178,6 +190,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN8_SBA_MOCS__MASK 0x000007f0 #define GEN8_SBA_MOCS__SHIFT 4 #define GEN6_SBA_ADDR_MODIFIED (0x1 << 0) +#define GEN8_SBA_SIZE__MASK 0xfffff000 +#define GEN8_SBA_SIZE__SHIFT 12 +#define GEN8_SBA_SIZE__SHR 12 +#define GEN8_SBA_SIZE_MODIFIED (0x1 << 0) #define GEN6_BINDING_TABLE_ADDR__MASK 0x0000ffe0 #define GEN6_BINDING_TABLE_ADDR__SHIFT 5 #define GEN6_BINDING_TABLE_ADDR__SHR 5 diff --git a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h index 52173fe5d07..c79a4f3a830 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h @@ -168,7 +168,6 @@ enum gen_sample_count { GEN8_NUMSAMPLES_2 = 0x1, GEN6_NUMSAMPLES_4 = 0x2, GEN7_NUMSAMPLES_8 = 0x3, - GEN8_NUMSAMPLES_16 = 0x4, }; enum gen_inputattr_select { @@ -297,11 +296,58 @@ enum gen_msrast_mode { #define GEN7_URB_DW1_OFFSET__MASK 0x3e000000 #define GEN7_URB_DW1_OFFSET__SHIFT 25 +#define GEN75_URB_DW1_OFFSET__MASK 0x7e000000 +#define GEN75_URB_DW1_OFFSET__SHIFT 25 +#define GEN8_URB_DW1_OFFSET__MASK 0xfe000000 +#define GEN8_URB_DW1_OFFSET__SHIFT 25 #define GEN7_URB_DW1_ENTRY_SIZE__MASK 0x01ff0000 #define GEN7_URB_DW1_ENTRY_SIZE__SHIFT 16 #define GEN7_URB_DW1_ENTRY_COUNT__MASK 0x0000ffff #define GEN7_URB_DW1_ENTRY_COUNT__SHIFT 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_ANY__SIZE 130 + + +#define GEN75_GATHER_CONST_DW1_BT_VALID__MASK 0xffff0000 +#define GEN75_GATHER_CONST_DW1_BT_VALID__SHIFT 16 +#define GEN75_GATHER_CONST_DW1_BT_BLOCK__MASK 0x0000f000 +#define GEN75_GATHER_CONST_DW1_BT_BLOCK__SHIFT 12 + +#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__MASK 0x007fffc0 +#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHIFT 6 +#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHR 6 +#define GEN8_GATHER_CONST_DW2_DX9_STALL (0x1 << 5) +#define GEN75_GATHER_CONST_DW2_DX9_ENABLE (0x1 << 4) + +#define GEN75_GATHER_CONST_DW_ENTRY_HIGH__MASK 0xffff0000 +#define GEN75_GATHER_CONST_DW_ENTRY_HIGH__SHIFT 16 +#define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__MASK 0x0000ff00 +#define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__SHIFT 8 +#define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__MASK 0x000000f0 +#define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__SHIFT 4 +#define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__MASK 0x0000001f +#define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__SHIFT 0 + +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_ANY__SIZE 258 + + +#define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__MASK 0xffff0000 +#define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__SHIFT 16 +#define GEN75_BT_EDIT_DW1_TARGET__MASK 0x00000003 +#define GEN75_BT_EDIT_DW1_TARGET__SHIFT 0 +#define GEN75_BT_EDIT_DW1_TARGET_CORE0 0x1 +#define GEN75_BT_EDIT_DW1_TARGET_CORE1 0x2 +#define GEN75_BT_EDIT_DW1_TARGET_ALL 0x3 + +#define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__MASK 0x00ff0000 +#define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__SHIFT 16 +#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK 0x0000ffff +#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT 0 +#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR 5 +#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK 0x0000ffff +#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT 0 +#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR 6 + #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE 2 @@ -315,6 +361,48 @@ enum gen_msrast_mode { #define GEN75_PCB_ALLOC_DW1_SIZE__MASK 0x0000003f #define GEN75_PCB_ALLOC_DW1_SIZE__SHIFT 0 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC__SIZE 3 + + +#define GEN75_BT_POOL_ALLOC_DW1_ADDR__MASK 0xfffff000 +#define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHIFT 12 +#define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHR 12 +#define GEN75_BT_POOL_ALLOC_DW1_ENABLE (0x1 << 11) +#define GEN75_BT_POOL_ALLOC_DW1_MOCS__MASK 0x00000780 +#define GEN75_BT_POOL_ALLOC_DW1_MOCS__SHIFT 7 +#define GEN8_BT_POOL_ALLOC_DW1_MOCS__MASK 0x0000007f +#define GEN8_BT_POOL_ALLOC_DW1_MOCS__SHIFT 0 + +#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__MASK 0xfffff000 +#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHIFT 12 +#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHR 12 + + +#define GEN8_BT_POOL_ALLOC_DW3_SIZE__MASK 0xfffff000 +#define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHIFT 12 +#define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHR 12 + +#define GEN75_3DSTATE_GATHER_POOL_ALLOC__SIZE 3 + + +#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__MASK 0xfffff000 +#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHIFT 12 +#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHR 12 +#define GEN75_GATHER_POOL_ALLOC_DW1_ENABLE (0x1 << 11) +#define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__MASK 0x0000000f +#define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT 0 +#define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__MASK 0x0000007f +#define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT 0 + +#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__MASK 0xfffff000 +#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHIFT 12 +#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHR 12 + + +#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__MASK 0xfffff000 +#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHIFT 12 +#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHR 12 + #define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE 133 @@ -402,15 +490,15 @@ enum gen_msrast_mode { #define GEN8_SGVS_DW1_IID_ENABLE (0x1 << 31) -#define GEN8_SGVS_DW1_IID_VE_COMP__MASK 0x60000000 -#define GEN8_SGVS_DW1_IID_VE_COMP__SHIFT 29 -#define GEN8_SGVS_DW1_IID_VE_INDEX__MASK 0x003f0000 -#define GEN8_SGVS_DW1_IID_VE_INDEX__SHIFT 16 +#define GEN8_SGVS_DW1_IID_COMP__MASK 0x60000000 +#define GEN8_SGVS_DW1_IID_COMP__SHIFT 29 +#define GEN8_SGVS_DW1_IID_OFFSET__MASK 0x003f0000 +#define GEN8_SGVS_DW1_IID_OFFSET__SHIFT 16 #define GEN8_SGVS_DW1_VID_ENABLE (0x1 << 15) -#define GEN8_SGVS_DW1_VID_VE_COMP__MASK 0x00006000 -#define GEN8_SGVS_DW1_VID_VE_COMP__SHIFT 13 -#define GEN8_SGVS_DW1_VID_VE_INDEX__MASK 0x0000003f -#define GEN8_SGVS_DW1_VID_VE_INDEX__SHIFT 0 +#define GEN8_SGVS_DW1_VID_COMP__MASK 0x00006000 +#define GEN8_SGVS_DW1_VID_COMP__SHIFT 13 +#define GEN8_SGVS_DW1_VID_OFFSET__MASK 0x0000003f +#define GEN8_SGVS_DW1_VID_OFFSET__SHIFT 0 #define GEN8_3DSTATE_VF_TOPOLOGY__SIZE 2 @@ -464,6 +552,10 @@ enum gen_msrast_mode { #define GEN7_3DSTATE_POINTERS_ANY__SIZE 2 +#define GEN7_PTR_DW1_ADDR__MASK 0xffffffe0 +#define GEN7_PTR_DW1_ADDR__SHIFT 5 +#define GEN7_PTR_DW1_ADDR__SHR 5 +#define GEN8_PTR_DW1_CHANGED (0x1 << 0) #define GEN6_3DSTATE_VS__SIZE 9 @@ -513,12 +605,14 @@ enum gen_msrast_mode { #define GEN8_VS_DW7_CACHE_DISABLE (0x1 << 1) #define GEN8_VS_DW7_VS_ENABLE (0x1 << 0) -#define GEN8_VS_DW8_URB_WRITE_OFFSET__MASK 0x03e00000 -#define GEN8_VS_DW8_URB_WRITE_OFFSET__SHIFT 21 -#define GEN8_VS_DW8_URB_WRITE_LEN__MASK 0x001f0000 -#define GEN8_VS_DW8_URB_WRITE_LEN__SHIFT 16 +#define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__MASK 0x07e00000 +#define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__SHIFT 21 +#define GEN8_VS_DW8_VUE_OUT_LEN__MASK 0x001f0000 +#define GEN8_VS_DW8_VUE_OUT_LEN__SHIFT 16 #define GEN8_VS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00 #define GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT 8 +#define GEN8_VS_DW8_UCP_CULL_ENABLES__MASK 0x000000ff +#define GEN8_VS_DW8_UCP_CULL_ENABLES__SHIFT 0 #define GEN7_3DSTATE_HS__SIZE 9 @@ -558,11 +652,11 @@ enum gen_msrast_mode { -#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x000000ff -#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0 #define GEN8_HS_DW2_HS_ENABLE (0x1 << 31) #define GEN8_HS_DW2_STATISTICS (0x1 << 29) +#define GEN8_HS_DW2_MAX_THREADS__MASK 0x0001ff00 +#define GEN8_HS_DW2_MAX_THREADS__SHIFT 8 #define GEN8_HS_DW2_INSTANCE_COUNT__MASK 0x0000000f #define GEN8_HS_DW2_INSTANCE_COUNT__SHIFT 0 @@ -584,9 +678,6 @@ enum gen_msrast_mode { #define GEN8_HS_DW7_URB_READ_OFFSET__MASK 0x000003f0 #define GEN8_HS_DW7_URB_READ_OFFSET__SHIFT 4 -#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__MASK 0x00001fff -#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHIFT 0 -#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHR 6 #define GEN7_3DSTATE_TE__SIZE 4 @@ -660,16 +751,19 @@ enum gen_msrast_mode { #define GEN8_DS_DW7_MAX_THREADS__MASK 0x3fe00000 #define GEN8_DS_DW7_MAX_THREADS__SHIFT 21 #define GEN8_DS_DW7_STATISTICS (0x1 << 10) +#define GEN8_DS_DW7_SIMD8_ENABLE (0x1 << 3) #define GEN8_DS_DW7_COMPUTE_W (0x1 << 2) #define GEN8_DS_DW7_CACHE_DISABLE (0x1 << 1) #define GEN8_DS_DW7_DS_ENABLE (0x1 << 0) -#define GEN8_DS_DW8_URB_WRITE_OFFSET__MASK 0x03e00000 -#define GEN8_DS_DW8_URB_WRITE_OFFSET__SHIFT 21 -#define GEN8_DS_DW8_URB_WRITE_LEN__MASK 0x001f0000 -#define GEN8_DS_DW8_URB_WRITE_LEN__SHIFT 16 +#define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__MASK 0x07e00000 +#define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__SHIFT 21 +#define GEN8_DS_DW8_VUE_OUT_LEN__MASK 0x001f0000 +#define GEN8_DS_DW8_VUE_OUT_LEN__SHIFT 16 #define GEN8_DS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00 #define GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT 8 +#define GEN8_DS_DW8_UCP_CULL_ENABLES__MASK 0x000000ff +#define GEN8_DS_DW8_UCP_CULL_ENABLES__SHIFT 0 @@ -771,7 +865,7 @@ enum gen_msrast_mode { #define GEN8_GS_DW1_KERNEL_ADDR__SHR 6 -#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK 0x0000007f +#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK 0x0000003f #define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__SHIFT 0 @@ -815,18 +909,20 @@ enum gen_msrast_mode { #define GEN8_GS_DW8_GSCTRL__SHIFT 31 #define GEN8_GS_DW8_GSCTRL_CUT (0x0 << 31) #define GEN8_GS_DW8_GSCTRL_SID (0x1 << 31) -#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__MASK 0x00001fff -#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHIFT 0 -#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHR 6 -#define GEN9_GS_DW8_MAX_THREADS__MASK 0x00001fff +#define GEN8_GS_DW8_STATIC_OUTPUT (0x1 << 30) +#define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__MASK 0x07ff0000 +#define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__SHIFT 16 +#define GEN9_GS_DW8_MAX_THREADS__MASK 0x000001ff #define GEN9_GS_DW8_MAX_THREADS__SHIFT 0 -#define GEN8_GS_DW9_URB_WRITE_OFFSET__MASK 0x03e00000 -#define GEN8_GS_DW9_URB_WRITE_OFFSET__SHIFT 21 -#define GEN8_GS_DW9_URB_WRITE_LEN__MASK 0x001f0000 -#define GEN8_GS_DW9_URB_WRITE_LEN__SHIFT 16 +#define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__MASK 0x07e00000 +#define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__SHIFT 21 +#define GEN8_GS_DW9_VUE_OUT_LEN__MASK 0x001f0000 +#define GEN8_GS_DW9_VUE_OUT_LEN__SHIFT 16 #define GEN8_GS_DW9_UCP_CLIP_ENABLES__MASK 0x0000ff00 #define GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT 8 +#define GEN8_GS_DW9_UCP_CULL_ENABLES__MASK 0x000000ff +#define GEN8_GS_DW9_UCP_CULL_ENABLES__SHIFT 0 #define GEN7_3DSTATE_STREAMOUT__SIZE 5 @@ -838,6 +934,11 @@ enum gen_msrast_mode { #define GEN7_SO_DW1_REORDER_MODE__MASK 0x04000000 #define GEN7_SO_DW1_REORDER_MODE__SHIFT 26 #define GEN7_SO_DW1_STATISTICS (0x1 << 25) +#define GEN8_SO_DW1_FORCE_RENDERING__MASK 0x01800000 +#define GEN8_SO_DW1_FORCE_RENDERING__SHIFT 23 +#define GEN8_SO_DW1_FORCE_RENDERING_NORMAL (0x0 << 23) +#define GEN8_SO_DW1_FORCE_RENDERING_OFF (0x2 << 23) +#define GEN8_SO_DW1_FORCE_RENDERING_ON (0x3 << 23) #define GEN7_SO_DW1_BUFFER_ENABLES__MASK 0x00000f00 #define GEN7_SO_DW1_BUFFER_ENABLES__SHIFT 8 @@ -928,9 +1029,9 @@ enum gen_msrast_mode { -#define GEN8_SO_BUF_DW5_OFFSET_ADDR__MASK 0xfffffffc -#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHIFT 2 -#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHR 2 +#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__MASK 0xfffffffc +#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHIFT 2 +#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHR 2 @@ -939,6 +1040,7 @@ enum gen_msrast_mode { #define GEN7_CLIP_DW1_FRONT_WINDING__MASK 0x00100000 #define GEN7_CLIP_DW1_FRONT_WINDING__SHIFT 20 +#define GEN8_CLIP_DW1_FORCE_UCP_CULL_ENABLES (0x1 << 20) #define GEN7_CLIP_DW1_SUBPIXEL__MASK 0x00080000 #define GEN7_CLIP_DW1_SUBPIXEL__SHIFT 19 #define GEN7_CLIP_DW1_SUBPIXEL_8BITS (0x0 << 19) @@ -946,6 +1048,8 @@ enum gen_msrast_mode { #define GEN7_CLIP_DW1_EARLY_CULL_ENABLE (0x1 << 18) #define GEN7_CLIP_DW1_CULL_MODE__MASK 0x00030000 #define GEN7_CLIP_DW1_CULL_MODE__SHIFT 16 +#define GEN8_CLIP_DW1_FORCE_UCP_CLIP_ENABLES (0x1 << 17) +#define GEN8_CLIP_DW1_FORCE_CLIP_MODE (0x1 << 16) #define GEN6_CLIP_DW1_STATISTICS (0x1 << 10) #define GEN6_CLIP_DW1_UCP_CULL_ENABLES__MASK 0x000000ff #define GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT 0 @@ -1026,6 +1130,7 @@ enum gen_msrast_mode { #define GEN7_SF_DW3_TRIFAN_PROVOKE__MASK 0x06000000 #define GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT 25 #define GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE (0x1 << 14) +#define GEN8_SF_DW3_SMOOTH_POINT_ENABLE (0x1 << 13) #define GEN7_SF_DW3_SUBPIXEL__MASK 0x00001000 #define GEN7_SF_DW3_SUBPIXEL__SHIFT 12 #define GEN7_SF_DW3_SUBPIXEL_8BITS (0x0 << 12) @@ -1037,8 +1142,8 @@ enum gen_msrast_mode { #define GEN7_3DSTATE_SBE_DW1__SIZE 13 -#define GEN8_SBE_DW1_USE_URB_READ_LEN (0x1 << 29) -#define GEN8_SBE_DW1_USE_URB_READ_OFFSET (0x1 << 28) +#define GEN8_SBE_DW1_FORCE_URB_READ_LEN (0x1 << 29) +#define GEN8_SBE_DW1_FORCE_URB_READ_OFFSET (0x1 << 28) #define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK 0x10000000 #define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT 28 #define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15 (0x0 << 28) @@ -1050,21 +1155,28 @@ enum gen_msrast_mode { #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__SHIFT 20 #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT (0x0 << 20) #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT (0x1 << 20) +#define GEN8_SBE_DW1_PID_OVERRIDE_W (0x1 << 19) +#define GEN8_SBE_DW1_PID_OVERRIDE_Z (0x1 << 18) +#define GEN8_SBE_DW1_PID_OVERRIDE_Y (0x1 << 17) +#define GEN8_SBE_DW1_PID_OVERRIDE_X (0x1 << 16) #define GEN7_SBE_DW1_URB_READ_LEN__MASK 0x0000f800 #define GEN7_SBE_DW1_URB_READ_LEN__SHIFT 11 #define GEN7_SBE_DW1_URB_READ_OFFSET__MASK 0x000003f0 #define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT 4 #define GEN8_SBE_DW1_URB_READ_OFFSET__MASK 0x000007e0 #define GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT 5 +#define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__MASK 0x0000001f +#define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__SHIFT 0 #define GEN8_3DSTATE_SBE_SWIZ_DW1_DW8__SIZE 8 #define GEN8_SBE_SWIZ_HIGH__MASK 0xffff0000 #define GEN8_SBE_SWIZ_HIGH__SHIFT 16 -#define GEN8_SBE_SWIZ_OVERRIDE_W (0x1 << 15) -#define GEN8_SBE_SWIZ_OVERRIDE_Z (0x1 << 14) -#define GEN8_SBE_SWIZ_OVERRIDE_Y (0x1 << 13) -#define GEN8_SBE_SWIZ_OVERRIDE_X (0x1 << 12) +#define GEN8_SBE_SWIZ_CONST_OVERRIDE_W (0x1 << 15) +#define GEN8_SBE_SWIZ_CONST_OVERRIDE_Z (0x1 << 14) +#define GEN8_SBE_SWIZ_CONST_OVERRIDE_Y (0x1 << 13) +#define GEN8_SBE_SWIZ_CONST_OVERRIDE_X (0x1 << 12) +#define GEN8_SBE_SWIZ_SWIZZLE_CONTROL (0x1 << 11) #define GEN8_SBE_SWIZ_CONST__MASK 0x00000600 #define GEN8_SBE_SWIZ_CONST__SHIFT 9 #define GEN8_SBE_SWIZ_CONST_0000 (0x0 << 9) @@ -1126,12 +1238,28 @@ enum gen_msrast_mode { #define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE (0x1 << 26) +#define GEN8_RASTER_DW1_API__MASK 0x00c00000 +#define GEN8_RASTER_DW1_API__SHIFT 22 +#define GEN8_RASTER_DW1_API_DX9_OGL (0x0 << 22) +#define GEN8_RASTER_DW1_API_DX10 (0x1 << 22) +#define GEN8_RASTER_DW1_API_DX10_1 (0x2 << 22) #define GEN8_RASTER_DW1_FRONT_WINDING__MASK 0x00200000 #define GEN8_RASTER_DW1_FRONT_WINDING__SHIFT 21 +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__MASK 0x001c0000 +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__SHIFT 18 +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_0 (0x0 << 18) +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_1 (0x1 << 18) +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_2 (0x2 << 18) +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_4 (0x3 << 18) +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_8 (0x4 << 18) +#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_16 (0x5 << 18) #define GEN8_RASTER_DW1_CULL_MODE__MASK 0x00030000 #define GEN8_RASTER_DW1_CULL_MODE__SHIFT 16 +#define GEN8_RASTER_DW1_FORCE_MULTISAMPLE_ENABLE (0x1 << 14) #define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE (0x1 << 13) -#define GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE (0x1 << 12) +#define GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE (0x1 << 12) +#define GEN8_RASTER_DW1_DX_MSRASTMODE__MASK 0x00000c00 +#define GEN8_RASTER_DW1_DX_MSRASTMODE__SHIFT 10 #define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID (0x1 << 9) #define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME (0x1 << 8) #define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT (0x1 << 7) @@ -1223,10 +1351,10 @@ enum gen_msrast_mode { #define GEN7_WM_DW1_STATISTICS (0x1 << 31) -#define GEN7_WM_DW1_DEPTH_CLEAR (0x1 << 30) +#define GEN7_WM_DW1_LEGACY_DEPTH_CLEAR (0x1 << 30) #define GEN7_WM_DW1_PS_DISPATCH_ENABLE (0x1 << 29) -#define GEN7_WM_DW1_DEPTH_RESOLVE (0x1 << 28) -#define GEN7_WM_DW1_HIZ_RESOLVE (0x1 << 27) +#define GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE (0x1 << 28) +#define GEN7_WM_DW1_LEGACY_HIZ_RESOLVE (0x1 << 27) #define GEN7_WM_DW1_LEGACY_LINE_RAST (0x1 << 26) #define GEN7_WM_DW1_PS_KILL_PIXEL (0x1 << 25) #define GEN7_WM_DW1_PSCDEPTH__MASK 0x01800000 @@ -1235,6 +1363,11 @@ enum gen_msrast_mode { #define GEN7_WM_DW1_EDSC__SHIFT 21 #define GEN7_WM_DW1_PS_USE_DEPTH (0x1 << 20) #define GEN7_WM_DW1_PS_USE_W (0x1 << 19) +#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__MASK 0x00180000 +#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__SHIFT 19 +#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_NORMAL (0x0 << 19) +#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_OFF (0x1 << 19) +#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_ON (0x2 << 19) #define GEN7_WM_DW1_ZW_INTERP__MASK 0x00060000 #define GEN7_WM_DW1_ZW_INTERP__SHIFT 17 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK 0x0001f800 @@ -1261,6 +1394,11 @@ enum gen_msrast_mode { #define GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT (0x1 << 2) #define GEN7_WM_DW1_MSRASTMODE__MASK 0x00000003 #define GEN7_WM_DW1_MSRASTMODE__SHIFT 0 +#define GEN8_WM_DW1_FORCE_KILL_PIXEL__MASK 0x00000003 +#define GEN8_WM_DW1_FORCE_KILL_PIXEL__SHIFT 0 +#define GEN8_WM_DW1_FORCE_KILL_PIXEL_NORMAL 0x0 +#define GEN8_WM_DW1_FORCE_KILL_PIXEL_OFF 0x1 +#define GEN8_WM_DW1_FORCE_KILL_PIXEL_ON 0x2 #define GEN7_WM_DW2_MSDISPMODE__MASK 0x80000000 #define GEN7_WM_DW2_MSDISPMODE__SHIFT 31 @@ -1271,6 +1409,7 @@ enum gen_msrast_mode { #define GEN8_3DSTATE_WM_CHROMAKEY__SIZE 2 +#define GEN8_CHROMAKEY_DW1_KILL_ENABLE (0x1 << 31) #define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE 4 @@ -1318,6 +1457,7 @@ enum gen_msrast_mode { #define GEN8_WM_HZ_DW1_STENCIL_CLEAR (0x1 << 31) #define GEN8_WM_HZ_DW1_DEPTH_CLEAR (0x1 << 30) +#define GEN8_WM_HZ_DW1_SCISSOR_ENABLE (0x1 << 29) #define GEN8_WM_HZ_DW1_DEPTH_RESOLVE (0x1 << 28) #define GEN8_WM_HZ_DW1_HIZ_RESOLVE (0x1 << 27) #define GEN8_WM_HZ_DW1_PIXEL_OFFSET_ENABLE (0x1 << 26) @@ -1443,17 +1583,17 @@ enum gen_msrast_mode { #define GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE (0x1 << 31) #define GEN8_PS_BLEND_DW1_WRITABLE_RT (0x1 << 30) -#define GEN8_PS_BLEND_DW1_BLEND_ENABLE (0x1 << 29) -#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__MASK 0x1f000000 -#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__SHIFT 24 -#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__MASK 0x00f80000 -#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__SHIFT 19 -#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__MASK 0x0007c000 -#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__SHIFT 14 -#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__MASK 0x00003e00 -#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__SHIFT 9 +#define GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE (0x1 << 29) +#define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__MASK 0x1f000000 +#define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT 24 +#define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__MASK 0x00f80000 +#define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT 19 +#define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__MASK 0x0007c000 +#define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT 14 +#define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__MASK 0x00003e00 +#define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT 9 #define GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE (0x1 << 8) -#define GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE (0x1 << 7) +#define GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE (0x1 << 7) #define GEN6_3DSTATE_CONSTANT_ANY__SIZE 11 @@ -1469,6 +1609,8 @@ enum gen_msrast_mode { #define GEN6_CONSTANT_DW_ADDR_ADDR__SHR 5 +#define GEN8_CONSTANT_DW0_MOCS__MASK 0x00007f00 +#define GEN8_CONSTANT_DW0_MOCS__SHIFT 8 #define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__MASK 0xffff0000 #define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__SHIFT 16 @@ -1502,6 +1644,8 @@ enum gen_msrast_mode { #define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE 4 +#define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__MASK 0x0000c000 +#define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__SHIFT 14 #define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__MASK 0xffff0000 #define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__SHIFT 16 @@ -1624,15 +1768,12 @@ enum gen_msrast_mode { #define GEN8_DEPTH_DW5_MOCS__MASK 0x0000007f #define GEN8_DEPTH_DW5_MOCS__SHIFT 0 -#define GEN8_DEPTH_DW6_OFFSET_Y__MASK 0xffff0000 -#define GEN8_DEPTH_DW6_OFFSET_Y__SHIFT 16 -#define GEN8_DEPTH_DW6_OFFSET_X__MASK 0x0000ffff -#define GEN8_DEPTH_DW6_OFFSET_X__SHIFT 0 #define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__MASK 0xffe00000 #define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__SHIFT 21 #define GEN8_DEPTH_DW7_QPITCH__MASK 0x00007fff #define GEN8_DEPTH_DW7_QPITCH__SHIFT 0 +#define GEN8_DEPTH_DW7_QPITCH__SHR 2 #define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE 2 @@ -1649,6 +1790,11 @@ enum gen_msrast_mode { #define GEN6_3DSTATE_LINE_STIPPLE__SIZE 3 +#define GEN6_LINE_STIPPLE_DW1_CURRENT_MODIFY_ENABLE (0x1 << 31) +#define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__MASK 0x3fe00000 +#define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__SHIFT 21 +#define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__MASK 0x000f0000 +#define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__SHIFT 16 #define GEN6_LINE_STIPPLE_DW1_PATTERN__MASK 0x0000ffff #define GEN6_LINE_STIPPLE_DW1_PATTERN__SHIFT 0 @@ -1664,16 +1810,28 @@ enum gen_msrast_mode { #define GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE 3 +#define GEN8_AA_LINE_DW1_POINT_BIAS__MASK 0xff000000 +#define GEN8_AA_LINE_DW1_POINT_BIAS__SHIFT 24 +#define GEN8_AA_LINE_DW1_POINT_BIAS__RADIX 8 #define GEN6_AA_LINE_DW1_BIAS__MASK 0x00ff0000 #define GEN6_AA_LINE_DW1_BIAS__SHIFT 16 #define GEN6_AA_LINE_DW1_BIAS__RADIX 8 +#define GEN8_AA_LINE_DW1_POINT_SLOPE__MASK 0x0000ff00 +#define GEN8_AA_LINE_DW1_POINT_SLOPE__SHIFT 8 +#define GEN8_AA_LINE_DW1_POINT_SLOPE__RADIX 8 #define GEN6_AA_LINE_DW1_SLOPE__MASK 0x000000ff #define GEN6_AA_LINE_DW1_SLOPE__SHIFT 0 #define GEN6_AA_LINE_DW1_SLOPE__RADIX 8 +#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__MASK 0xff000000 +#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__SHIFT 24 +#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__RADIX 8 #define GEN6_AA_LINE_DW2_CAP_BIAS__MASK 0x00ff0000 #define GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT 16 #define GEN6_AA_LINE_DW2_CAP_BIAS__RADIX 8 +#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__MASK 0x0000ff00 +#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__SHIFT 8 +#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__RADIX 8 #define GEN6_AA_LINE_DW2_CAP_SLOPE__MASK 0x000000ff #define GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT 0 #define GEN6_AA_LINE_DW2_CAP_SLOPE__RADIX 8 @@ -1690,7 +1848,7 @@ enum gen_msrast_mode { #define GEN6_3DSTATE_MULTISAMPLE__SIZE 4 -#define GEN75_MULTISAMPLE_DW1_DX9_MULTISAMPLE_ENABLE (0x1 << 5) +#define GEN75_MULTISAMPLE_DW1_PIXEL_OFFSET_ENABLE (0x1 << 5) #define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__MASK 0x00000010 #define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT 4 #define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__MASK 0x0000000e @@ -1724,6 +1882,7 @@ enum gen_msrast_mode { #define GEN8_STENCIL_DW4_QPITCH__MASK 0x00007fff #define GEN8_STENCIL_DW4_QPITCH__SHIFT 0 +#define GEN8_STENCIL_DW4_QPITCH__SHR 2 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE 5 @@ -1739,6 +1898,7 @@ enum gen_msrast_mode { #define GEN8_HIZ_DW4_QPITCH__MASK 0x00007fff #define GEN8_HIZ_DW4_QPITCH__SHIFT 0 +#define GEN8_HIZ_DW4_QPITCH__SHR 2 #define GEN6_3DSTATE_CLEAR_PARAMS__SIZE 3 diff --git a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h index b65b704adc6..b2c2142af78 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h @@ -430,8 +430,10 @@ enum gen_key_filter { #define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9 (0x1 << 29) #define GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28) #define GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL (0x1 << 27) -#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_ENABLE__MASK 0x18000000 -#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_ENABLE__SHIFT 27 +#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE__MASK 0x18000000 +#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE__SHIFT 27 +#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE_NONE (0x0 << 27) +#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE_OGL (0x2 << 27) #define GEN6_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000 #define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT 22 #define GEN6_SAMPLER_DW0_BASE_LOD__RADIX 1 @@ -493,23 +495,11 @@ enum gen_key_filter { #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5 -#define GEN8_SAMPLER_DW2_SEP_FILTER_COEFF_TABLE_SIZE__MASK 0xc0000000 -#define GEN8_SAMPLER_DW2_SEP_FILTER_COEFF_TABLE_SIZE__SHIFT 30 -#define GEN8_SAMPLER_DW2_SEP_FILTER_WIDTH__MASK 0x30000000 -#define GEN8_SAMPLER_DW2_SEP_FILTER_WIDTH__SHIFT 28 -#define GEN8_SAMPLER_DW2_SEP_FILTER_HEIGHT__MASK 0x0c000000 -#define GEN8_SAMPLER_DW2_SEP_FILTER_HEIGHT__SHIFT 26 #define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__MASK 0x00ffffc0 #define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHIFT 6 #define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHR 6 -#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_MODE (0x1 << 4) -#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_COEFF_SIZE (0x1 << 3) -#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_HALIGN (0x1 << 2) -#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_VALIGN (0x1 << 1) #define GEN8_SAMPLER_DW2_LOD_CLAMP_MAG_MODE (0x1 << 0) -#define GEN8_SAMPLER_DW3_NON_SEP_FILTER_FOOTPRINT_MASK__MASK 0xff000000 -#define GEN8_SAMPLER_DW3_NON_SEP_FILTER_FOOTPRINT_MASK__SHIFT 24 #define GEN6_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25) #define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000 #define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23 diff --git a/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h index 55d830bad32..2476002ec91 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h @@ -111,6 +111,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN8_IDRT_DW5_CURBE_READ_LEN__MASK 0xffff0000 #define GEN8_IDRT_DW5_CURBE_READ_LEN__SHIFT 16 +#define GEN8_IDRT_DW5_CURBE_READ_OFFSET__MASK 0x0000ffff +#define GEN8_IDRT_DW5_CURBE_READ_OFFSET__SHIFT 0 #define GEN8_IDRT_DW6_ROUNDING_MODE__MASK 0x00c00000 #define GEN8_IDRT_DW6_ROUNDING_MODE__SHIFT 22 @@ -121,7 +123,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN8_IDRT_DW6_BARRIER_ENABLE (0x1 << 21) #define GEN8_IDRT_DW6_SLM_SIZE__MASK 0x001f0000 #define GEN8_IDRT_DW6_SLM_SIZE__SHIFT 16 -#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK 0x000000ff +#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK 0x000003ff #define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__SHIFT 0 #define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff @@ -280,6 +282,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN8_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f #define GEN8_GPGPU_DW1_IDRT_OFFSET__SHIFT 0 +#define GEN8_GPGPU_DW2_INDIRECT_LEN__MASK 0x0001ffff +#define GEN8_GPGPU_DW2_INDIRECT_LEN__SHIFT 0 #define GEN8_GPGPU_DW3_INDIRECT_ADDR__MASK 0xffffffe0 #define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHIFT 5 diff --git a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h index b5d09f64429..c180450ce27 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h @@ -388,7 +388,7 @@ enum gen_surface_scs { #define GEN8_SURFACE_DW0_TILING__SHIFT 12 #define GEN8_SURFACE_DW0_VSTRIDE (0x1 << 11) #define GEN8_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 10) -#define GEN8_SURFACE_DW0_SAMPLER_L2_BYPASS_MODE (0x1 << 9) +#define GEN8_SURFACE_DW0_SAMPLER_L2_BYPASS_DISABLE (0x1 << 9) #define GEN7_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8) #define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0 #define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6 @@ -402,6 +402,7 @@ enum gen_surface_scs { #define GEN8_SURFACE_DW1_BASE_LOD__SHIFT 19 #define GEN8_SURFACE_DW1_QPITCH__MASK 0x00007fff #define GEN8_SURFACE_DW1_QPITCH__SHIFT 0 +#define GEN8_SURFACE_DW1_QPITCH__SHR 2 #define GEN7_SURFACE_DW2_HEIGHT__MASK 0x3fff0000 #define GEN7_SURFACE_DW2_HEIGHT__SHIFT 16 @@ -434,7 +435,6 @@ enum gen_surface_scs { #define GEN8_SURFACE_DW4_MULTISAMPLECOUNT_2 (0x1 << 3) #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 3) #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8 (0x3 << 3) -#define GEN8_SURFACE_DW4_MULTISAMPLECOUNT_16 (0x4 << 3) #define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007 #define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT 0 #define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__MASK 0x07ffffff @@ -451,8 +451,11 @@ enum gen_surface_scs { #define GEN8_SURFACE_DW5_Y_OFFSET__MASK 0x00e00000 #define GEN8_SURFACE_DW5_Y_OFFSET__SHIFT 21 #define GEN8_SURFACE_DW5_Y_OFFSET__SHR 1 -#define GEN8_SURFACE_DW5_CUBE_EWA (0x1 << 20) -#define GEN8_SURFACE_DW5_COHERENCY_TYPE (0x1 << 14) +#define GEN8_SURFACE_DW5_CUBE_EWA_DISABLE (0x1 << 20) +#define GEN8_SURFACE_DW5_COHERENCY_TYPE__MASK 0x00004000 +#define GEN8_SURFACE_DW5_COHERENCY_TYPE__SHIFT 14 +#define GEN8_SURFACE_DW5_COHERENCY_TYPE_GPU (0x0 << 14) +#define GEN8_SURFACE_DW5_COHERENCY_TYPE_IA (0x1 << 14) #define GEN7_SURFACE_DW5_MIN_LOD__MASK 0x000000f0 #define GEN7_SURFACE_DW5_MIN_LOD__SHIFT 4 #define GEN7_SURFACE_DW5_MIP_COUNT_LOD__MASK 0x0000000f @@ -463,22 +466,23 @@ enum gen_surface_scs { #define GEN7_SURFACE_DW6_UV_X_OFFSET__SHIFT 16 #define GEN7_SURFACE_DW6_UV_Y_OFFSET__MASK 0x00003fff #define GEN7_SURFACE_DW6_UV_Y_OFFSET__SHIFT 0 +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0 +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6 +#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6 #define GEN7_SURFACE_DW6_MCS_ADDR__MASK 0xfffff000 #define GEN7_SURFACE_DW6_MCS_ADDR__SHIFT 12 #define GEN7_SURFACE_DW6_MCS_ADDR__SHR 12 #define GEN8_SURFACE_DW6_AUX_QPITCH__MASK 0x7fff0000 #define GEN8_SURFACE_DW6_AUX_QPITCH__SHIFT 16 +#define GEN8_SURFACE_DW6_AUX_QPITCH__SHR 2 #define GEN7_SURFACE_DW6_AUX_PITCH__MASK 0x00000ff8 #define GEN7_SURFACE_DW6_AUX_PITCH__SHIFT 3 -#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0 -#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6 -#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6 -#define GEN7_SURFACE_DW6_AUX_MODE__MASK 0x00000007 -#define GEN7_SURFACE_DW6_AUX_MODE__SHIFT 0 -#define GEN7_SURFACE_DW6_AUX_MODE_NONE 0x0 -#define GEN7_SURFACE_DW6_AUX_MODE_MCS 0x1 -#define GEN7_SURFACE_DW6_AUX_MODE_APPEND 0x2 -#define GEN8_SURFACE_DW6_AUX_MODE_HIZ 0x3 +#define GEN7_SURFACE_DW6_AUX__MASK 0x00000007 +#define GEN7_SURFACE_DW6_AUX__SHIFT 0 +#define GEN7_SURFACE_DW6_AUX_NONE 0x0 +#define GEN7_SURFACE_DW6_AUX_MCS 0x1 +#define GEN7_SURFACE_DW6_AUX_APPEND 0x2 +#define GEN8_SURFACE_DW6_AUX_HIZ 0x3 #define GEN7_SURFACE_DW7_CC_R__MASK 0x80000000 #define GEN7_SURFACE_DW7_CC_R__SHIFT 31 @@ -504,6 +508,12 @@ enum gen_surface_scs { +#define GEN8_SURFACE_DW11_V_X_OFFSET__MASK 0x3fff0000 +#define GEN8_SURFACE_DW11_V_X_OFFSET__SHIFT 16 +#define GEN8_SURFACE_DW11_V_Y_OFFSET__MASK 0x00003fff +#define GEN8_SURFACE_DW11_V_Y_OFFSET__SHIFT 0 +#define GEN8_SURFACE_DW11_AUX_ADDR_HI__MASK 0xffffffff +#define GEN8_SURFACE_DW11_AUX_ADDR_HI__SHIFT 0