From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Jul 2021 14:17:35 +0000 (+0100)
Subject: add TEMPORARY svremap form and instruction
X-Git-Tag: xlen-bcd~355
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c815bf79322e2a7f797c994c15ca7cdb8da8e313;p=openpower-isa.git

add TEMPORARY svremap form and instruction
---

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index d939625a..a46299e8 100644
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -275,6 +275,10 @@
    | PO   |   RT  |   RA | RC  | SVDS |  XO    |
    | PO   |   RS  |   RA | RC  | SVDS |  XO    |
 
+# 1.6.33 SVM-FORM
+   |0     |6        |11      |16     |21    |31  |
+   | PO   |  SVxd   |   SXyd |  SVRM |   XO |  / |
+
 # 1.6.28 Instruction Fields
     A (6)
         Field used by the tbegin. instruction to specify an
@@ -757,6 +761,15 @@
     SVi (16:23)
          Simple-V immediate field for setting VL or MVL
          Formats: SVL
+    SVRM (16:20)
+         Simple-V "REMAP" Mode
+         Formats: SVM
+    SVxd (6:10)
+         Simple-V "REMAP" x-dimension size
+         Formats: SVM
+    SVyd (11:15)
+         Simple-V "REMAP" y-dimension size
+         Formats: SVM
     SX,S (28,6:10)
          Fields SX and S are concatenated to specify a
          VSR to be used as a source.
diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index ab84b379..30c537fe 100644
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -1,2 +1,3 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS
 0b00000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,
+0b00001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svremap,SVM,
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index bf573899..37f14d1e 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -118,6 +118,7 @@ class Form(Enum):
     SVL = 29  # Simple-V for setvl instruction
     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
+    SVM = 32  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -383,6 +384,7 @@ class MicrOp(Enum):
     OP_FPOP = 77  # temporary: replace with actual ops
     OP_FPOP_I = 78 # temporary: replace with actual ops
     OP_FP_MADD = 79
+    OP_SVREMAP = 80
 
 
 @unique