From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jun 2022 09:56:25 +0000 (+0100)
Subject: Revert ""
X-Git-Tag: opf_rfc_ls005_v1~1611
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c82a2ae98bab629bc135f41c7c00a79a9a5b2f7e;p=libreriscv.git

Revert ""

This reverts commit 962dce9a0a139a516907f4a9bd640f60b6279440.
---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 4283e0769..303356e25 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -43,8 +43,9 @@ The Mode table for Arithmetic and Logical operations
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
 | 00  |   0 |  dz  sz | normal mode                      |
-| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce) |
-| 00  |   1 | 1  /    | parallel reduce mode (mapreduce) |
+| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
+| 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
+| 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
@@ -58,6 +59,7 @@ Fields:
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1
+* **SVM** sets "subvector" reduce mode
 * **N** sets signed/unsigned saturation.
 * **RC1** as if Rc=1, stores CRs *but not the result*
 * **VLi** VL inclusive: in fail-first mode, the truncation of