From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Nov 2021 16:23:12 +0000 (+0000)
Subject: rename instruction_active to instr_active in core
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c82b98279300c7cd918cd8b0cd052a35790ffa0b;p=soc.git

rename instruction_active to instr_active in core
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 82525d25..604624c4 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -247,7 +247,7 @@ class NonProductionCore(ControlBase):
         # or if the instruction could not be delivered, keep dropping the
         # latched copy into ireg
         ilatch = self.ispec()
-        self.instruction_active = Signal()
+        self.instr_active = Signal()
 
         # enable/busy-signals for each FU, get one bit for each FU (by name)
         fu_enable = Signal(len(fus), reset_less=True)
@@ -290,7 +290,7 @@ class NonProductionCore(ControlBase):
                 fnunit = fu.fnunit.value
                 en_req = Signal(name="issue_en_%s" % funame, reset_less=True)
                 fnmatch = (self.ireg.e.do.fn_unit & fnunit).bool()
-                comb += en_req.eq(fnmatch & ~fu.busy_o & self.instruction_active)
+                comb += en_req.eq(fnmatch & ~fu.busy_o & self.instr_active)
                 i_l.append(en_req) # store in list for doing the Cat-trick
                 # picker output, gated by enable: store in fu_bitdict
                 po = Signal(name="o_issue_pick_"+funame) # picker output
@@ -322,7 +322,7 @@ class NonProductionCore(ControlBase):
         with m.FSM():
             with m.State("READY"):
                 with m.If(self.p.i_valid): # run only when valid
-                    comb += self.instruction_active.eq(1)
+                    comb += self.instr_active.eq(1)
                     with m.Switch(self.ireg.e.do.insn_type):
                         # check for ATTN: halt if true
                         with m.Case(MicrOp.OP_ATTN):
@@ -363,7 +363,7 @@ class NonProductionCore(ControlBase):
                                 m.next = "WAITING"
 
             with m.State("WAITING"):
-                comb += self.instruction_active.eq(1)
+                comb += self.instr_active.eq(1)
                 with m.If(fu_found):
                     sync += l_issue_conflict.eq(0)
                 comb += self.p.o_ready.eq(0)
@@ -517,7 +517,7 @@ class NonProductionCore(ControlBase):
                 wvchk_en = Signal(len(wvchk.ren), name="wv_chk_addr_en_"+name)
                 issue_active = Signal(name="rd_iactive_"+name)
                 # XXX combinatorial loop here
-                #comb += issue_active.eq(self.instruction_active & rdflags[i])
+                #comb += issue_active.eq(self.instr_active & rdflags[i])
                 with m.If(issue_active):
                     if rfile.unary:
                         comb += wvchk_en.eq(read)