From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 7 Feb 2015 23:48:23 +0000 (+0100)
Subject: Fixed a bug with autowire bit size
X-Git-Tag: yosys-0.5~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8305e3a6d1e195391eb6962aac5bf7e1c548b5d;p=yosys.git

Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 17d62d4dd..f48101934 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1294,15 +1294,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// add entries to current_module->connections for assignments (outside of always blocks)
 	case AST_ASSIGN:
 		{
-			if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
-				RTLIL::SigSpec right = children[1]->genRTLIL();
-				RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size());
-				current_module->connect(RTLIL::SigSig(left, right));
-			} else {
-				RTLIL::SigSpec left = children[0]->genRTLIL();
-				RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
-				current_module->connect(RTLIL::SigSig(left, right));
-			}
+			RTLIL::SigSpec left = children[0]->genRTLIL();
+			RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
+			current_module->connect(RTLIL::SigSig(left, right));
 		}
 		break;