From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 01:08:46 +0000 (-0700)
Subject: Fix width of D
X-Git-Tag: working-ls180~1039^2~76
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c83a66755553f47f40c591110e6bdcd722360d6c;p=yosys.git

Fix width of D
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 3cfaa9371..adc09a6e4 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -48,7 +48,7 @@ static Cell* addDsp(Module *module) {
 	cell->setParam(ID(USE_SIMD), Const("ONE48"));
 	cell->setParam(ID(USE_DPORT), Const("FALSE"));
 
-	cell->setPort(ID(D), Const(0, 24));
+	cell->setPort(ID(D), Const(0, 25));
 	cell->setPort(ID(INMODE), Const(0, 5));
 	cell->setPort(ID(ALUMODE), Const(0, 4));
 	cell->setPort(ID(OPMODE), Const(0, 7));