From: whitequark <cz@m-labs.hk>
Date: Fri, 14 Dec 2018 05:17:43 +0000 (+0000)
Subject: back.pysim: delay clock processes by one half period.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c85382a022e0665c08d9e2d6f4fc29be39437afe;p=nmigen.git

back.pysim: delay clock processes by one half period.

Makes it easier to see initial delta cycles.
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 3975443..478a738 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -231,6 +231,7 @@ class Simulator:
         half_period = period / 2
         def clk_process():
             yield Passive()
+            yield Delay(half_period)
             while True:
                 yield clk.eq(1)
                 yield Delay(half_period)