From: Uros Bizjak Date: Mon, 2 May 2016 18:52:33 +0000 (+0200) Subject: predicates.md (register_ssemem_operand): New predicate. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8802daf944a9a46330d352ca6cdf147eb9770b8;p=gcc.git predicates.md (register_ssemem_operand): New predicate. * config/i386/predicates.md (register_ssemem_operand): New predicate. * config/i386/i386.md (*cmpi): Merge from *cmpi_mixed and *cmpi_i387. Disable unsupported alternatives using "enabled" attribute. Use register_ssemem_operand as operand 1 predicate. (*cmpixf_i387): Split XFmode pattern from *cmpi_i387. (*absneg2): Merge from *absneg2_mixed and *absneg2_i387. Disable unsupported alternatives using "enabled" attribute. From-SVN: r235782 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a527809c79c..ab057e97be0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2016-05-02 Uros Bizjak + + * config/i386/predicates.md (register_ssemem_operand): New predicate. + * config/i386/i386.md (*cmpi): Merge from + *cmpi_mixed and + *cmpi_i387. Disable unsupported + alternatives using "enabled" attribute. Use register_ssemem_operand + as operand 1 predicate. + (*cmpixf_i387): Split XFmode pattern from + *cmpi_i387. + (*absneg2): Merge from *absneg2_mixed and + *absneg2_i387. Disable unsupported alternatives using + "enabled" attribute. + 2016-05-02 Nathan Sidwell * omp-low.c (lower_oacc_head_tail): Assert there is at least one @@ -97,8 +111,6 @@ Disable unsupported alternatives using "enabled" attribute. Use nonimm_ssenomem_operand as operand 1 predicate. Also check X87_ENABLE_ARITH for TARGET_MIX_SSE_I387 alternatives. - * config/i386/predicates.md (nonimm_ssenomem_operand): New predicate. - (register_mixssei387nonimm_operand): Remove predicate. 2016-05-02 Richard Sandiford diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f4d33c59551..c409872a0be 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1665,12 +1665,13 @@ (define_mode_iterator FPCMP [CCFP CCFPU]) (define_mode_attr unord [(CCFP "") (CCFPU "u")]) -(define_insn "*cmpi_mixed" +(define_insn "*cmpi" [(set (reg:FPCMP FLAGS_REG) (compare:FPCMP (match_operand:MODEF 0 "register_operand" "f,v") - (match_operand:MODEF 1 "nonimmediate_operand" "f,vm")))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" + (match_operand:MODEF 1 "register_ssemem_operand" "f,vm")))] + "(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || (TARGET_80387 && TARGET_CMOVE)" "* return output_fp_compare (insn, operands, true, mode == CCFPUmode);" [(set_attr "type" "fcmp,ssecomi") @@ -1689,22 +1690,27 @@ (set_attr "bdver1_decode" "double") (set_attr "znver1_decode" "double") (set (attr "enabled") - (cond [(eq_attr "alternative" "0") - (symbol_ref "TARGET_MIX_SSE_I387") - ] - (symbol_ref "true")))]) + (if_then_else + (match_test ("SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")) + (if_then_else + (eq_attr "alternative" "0") + (symbol_ref "TARGET_MIX_SSE_I387") + (symbol_ref "true")) + (if_then_else + (eq_attr "alternative" "0") + (symbol_ref "true") + (symbol_ref "false"))))]) -(define_insn "*cmpi_i387" +(define_insn "*cmpixf_i387" [(set (reg:FPCMP FLAGS_REG) (compare:FPCMP - (match_operand:X87MODEF 0 "register_operand" "f") - (match_operand:X87MODEF 1 "register_operand" "f")))] - "TARGET_80387 && TARGET_CMOVE - && !(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" + (match_operand:XF 0 "register_operand" "f") + (match_operand:XF 1 "register_operand" "f")))] + "TARGET_80387 && TARGET_CMOVE" "* return output_fp_compare (insn, operands, true, - mode == CCFPUmode);" + mode == CCFPUmode);" [(set_attr "type" "fcmp") - (set_attr "mode" "") + (set_attr "mode" "XF") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "direct") (set_attr "bdver1_decode" "double") @@ -9235,27 +9241,34 @@ "TARGET_80387 || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") -(define_insn "*absneg2_mixed" +(define_insn "*absneg2" [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r") (match_operator:MODEF 3 "absneg_operator" [(match_operand:MODEF 1 "register_operand" "0,x,0,0")])) (use (match_operand: 2 "nonimmediate_operand" "xm,0,X,X")) (clobber (reg:CC FLAGS_REG))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" + "(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || TARGET_80387" "#" [(set (attr "enabled") - (cond [(eq_attr "alternative" "2") - (symbol_ref "TARGET_MIX_SSE_I387") - ] - (symbol_ref "true")))]) + (if_then_else + (match_test ("SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")) + (if_then_else + (eq_attr "alternative" "2") + (symbol_ref "TARGET_MIX_SSE_I387") + (symbol_ref "true")) + (if_then_else + (eq_attr "alternative" "2,3") + (symbol_ref "true") + (symbol_ref "false"))))]) -(define_insn "*absneg2_i387" - [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r") - (match_operator:X87MODEF 3 "absneg_operator" - [(match_operand:X87MODEF 1 "register_operand" "0,0")])) +(define_insn "*absnegxf2_i387" + [(set (match_operand:XF 0 "register_operand" "=f,!r") + (match_operator:XF 3 "absneg_operator" + [(match_operand:XF 1 "register_operand" "0,0")])) (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] - "TARGET_80387 && !(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" + "TARGET_80387" "#") (define_expand "tf2" diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index fe9bb2bc695..c1541b56d13 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -121,6 +121,13 @@ (match_operand 0 "nonmemory_operand") (match_operand 0 "general_operand"))) +;; Match register operands, but include memory operands for TARGET_SSE_MATH. +(define_predicate "register_ssemem_operand" + (if_then_else + (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH") + (match_operand 0 "nonimmediate_operand") + (match_operand 0 "register_operand"))) + ;; Match nonimmediate operands, but exclude memory operands ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled. (define_predicate "nonimm_ssenomem_operand"