From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 30 Apr 2013 16:55:01 +0000 (+0200)
Subject: actorlib/spi: add DMA read controller
X-Git-Tag: 24jan2021_ls180~2099^2~591
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8810a016f412bf786d92e4d9c5a479df4a77f3e;p=litex.git

actorlib/spi: add DMA read controller
---

diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py
index d136f97c..3ad45e26 100644
--- a/migen/actorlib/spi.py
+++ b/migen/actorlib/spi.py
@@ -4,6 +4,9 @@ from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
 from migen.bank.description import *
 from migen.flow.actor import *
+from migen.flow.network import *
+from migen.flow import plumbing
+from migen.actorlib import misc
 
 # layout is a list of tuples, either:
 # - (name, nbits, [reset value], [alignment bits])
@@ -111,3 +114,29 @@ class Collector(Module, AutoCSR):
 			rp.adr.eq(self._r_ra.storage),
 			self._r_rd.status.eq(rp.dat_r)
 		]
+
+class DMAReadController(Module):
+	def __init__(self, bus_accessor, mode, base_reset=0, length_reset=0):
+		bus_aw = len(bus_accessor.address.payload.a)
+		bus_dw = len(bus_accessor.data.payload.d)
+		alignment_bits = bits_for(bus_dw//8) - 1
+
+		layout = [
+			("length", bus_aw + alignment_bits, length_reset, alignment_bits),
+			("base", bus_aw + alignment_bits, base_reset, alignment_bits)
+		]
+		self.generator = SingleGenerator(layout, mode)
+		g = DataFlowGraph()
+		g.add_pipeline(self.generator,
+			misc.IntSequence(bus_aw, bus_aw),
+			AbstractActor(plumbing.Buffer),
+			bus_accessor,
+			AbstractActor(plumbing.Buffer))
+		comp_actor = CompositeActor(g)
+		self.submodules += comp_actor
+
+		self.data = comp_actor.q
+		self.busy = comp_actor.busy
+		
+	def get_csrs(self):
+		return self.generator.get_csrs()