From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 23:12:10 +0000 (+0100)
Subject: whoops broke downconvert rounding
X-Git-Tag: ls180-24jan2020~588
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c881264730440f5b5391da2ae028ee3c49ae3ade;p=ieee754fpu.git

whoops broke downconvert rounding
---

diff --git a/src/ieee754/fcvt/downsize.py b/src/ieee754/fcvt/downsize.py
index 2e61dcfb..b76e3f5e 100644
--- a/src/ieee754/fcvt/downsize.py
+++ b/src/ieee754/fcvt/downsize.py
@@ -108,7 +108,7 @@ class FPCVTDownConvertMod(PipeModBase):
             mo = Signal(self.o.z.m_width-1)
             comb += mo.eq(a1.m[ms:me])
             with m.If(self.o.of.roundz):
-                with m.If((mo.bool())):  # mantissa-out is all 1s
+                with m.If(((~mo).bool())):  # mantissa-out is all 1s
                     comb += self.o.z.create(a1.s, a1.e, mo+1)
                 with m.Else():
                     comb += self.o.z.create(a1.s, a1.e+1, mo+1)
diff --git a/src/ieee754/fcvt/test/fcvt_data_32_16.py b/src/ieee754/fcvt/test/fcvt_data_32_16.py
index 7be0829a..ed960a3f 100644
--- a/src/ieee754/fcvt/test/fcvt_data_32_16.py
+++ b/src/ieee754/fcvt/test/fcvt_data_32_16.py
@@ -14,4 +14,4 @@ def regressions():
     yield 0x358637BD,
     yield 0x3340f2a7,
     yield 0x33D6BF95,
-
+    yield 0x40801d50,