From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 10:36:34 +0000 (+0100)
Subject: add reconfigureable Load/Store class
X-Git-Tag: div_pipeline~269
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c88f971a7de1e8f6c0d5e8f56b1b0d44b3a92b3f;p=soc.git

add reconfigureable Load/Store class
---

diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py
new file mode 100644
index 00000000..8291276a
--- /dev/null
+++ b/src/soc/config/loadstore.py
@@ -0,0 +1,20 @@
+"""ConfigureableLoadStoreUnit
+
+allows the type of LoadStoreUnit to be run-time selectable
+
+"""
+from soc.experiment.pimem import TestMemoryLoadStoreUnit
+from soc.minerva.units.loadstore import BareLoadStoreUnit, CacheLoadStoreUnit
+
+
+class ConfigureableLoadStoreUnit:
+    def __init__(self, pspec):
+        lsidict = {'testmem': TestMemoryLoadStoreUnit,
+                   'bare_wb': BareLoadStoreUnit,
+                   'cache_wb': CacheLoadStoreUnit # TODO dcache parameters
+                  }
+        lsikls = lsidict[pspec.ldst_ifacetype]
+        self.lsi = lsikls(addr_wid=pspec.addr_wid,
+                          mask_wid=pspec.mask_wid, # cache line range
+                          data_wid=pspec.reg_wid)
+